- enable_pll();
-
- // PWM channel D is inverted, ...
- TCCR1C = _BV(COM1D1) | _BV(COM1D0) | _BV(PWM1D);
- // PWM channels A and B are not
- TCCR1A = _BV(COM1A1) | _BV(COM1B1) | _BV(PWM1A) | _BV(PWM1B);
- TCCR1D = 0;
- TCCR1B = _BV(CS10); // no clock prescaling
-
- TC1H = PWM_TOP >> 8;
- OCR1C = PWM_TOP & 0xFF; // TOP value
-
- TC1H = PWM_TOP >> 8; // PWM3 is inverted
- OCR1D = PWM_TOP & 0xFF;
-
- TC1H = 0x00;
- OCR1B = OCR1A = 0; // initial stride is 0
-
- DDRB &= ~(_BV( PB1 ) | _BV( PB3 ) | _BV( PB5 )); // tristate it
- PORTB &= ~(_BV( PB1 ) | _BV( PB3 ) | _BV( PB5 )); // set to zero