+ ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
+ pwm[n] = stride;
+ channels_running |= (1 << n);
+
+ if (!pll_enabled) {
+ power_timer1_enable();
+ enable_pll();
+ }
+
+ pwm_update_hw(n);
+
+ switch(n) {
+ case 0: DDRB |= _BV(PB1); break;
+ case 1: DDRB |= _BV(PB3); break;
+ case 2: DDRB |= _BV(PB5); break;
+ }
+ }