2 #include <avr/interrupt.h>
3 #include <util/delay.h>
4 #include <util/atomic.h>
8 static uint16_t pwm[N_PWMLEDS];
9 static volatile unsigned char step;
11 static void enable_pll()
16 /* Synchronize to the phase lock */
18 while ((PLLCSR & _BV(PLOCK)) == 0)
29 for (i = 0; i < N_PWMLEDS; i++)
34 // PWM channel D is inverted, ...
35 TCCR1C = _BV(COM1D1) | _BV(COM1D0) | _BV(PWM1D);
36 // PWM channels A and B are not
37 TCCR1A = _BV(COM1A1) | _BV(COM1B1) | _BV(PWM1A) | _BV(PWM1B);
39 TCCR1B = _BV(CS10); // no clock prescaling
42 OCR1C = PWM_MAX & 0xFF; // TOP value
44 TC1H = PWM_MAX >> 8; // PWM3 is inverted
45 OCR1D = PWM_MAX & 0xFF;
48 OCR1B = OCR1A = 0; // initial stride is 0
50 DDRB &= ~(_BV( PB1 ) | _BV( PB3 ) | _BV( PB5 )); // tristate it
51 PORTB &= ~(_BV( PB1 ) | _BV( PB3 ) | _BV( PB5 )); // set to zero
58 for (i = 0; i < N_PWMLEDS; i++)
61 DDRB &= ~(_BV( PB1 ) | _BV( PB3 ) | _BV( PB5 ));
62 TCCR1D = TCCR1C = TCCR1B = TCCR1A = 0;
66 PLLCSR &= ~(_BV(PLLE) | _BV(PCKE));
69 void pwm_off(unsigned char n)
71 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
75 case 0: DDRB &= ~_BV(PB1); break;
76 case 1: DDRB &= ~_BV(PB3); break;
77 case 2: DDRB &= ~_BV(PB5); break;
82 static void pwm_update_hw(unsigned char n)
85 uint16_t stride = (pwm[n] + step) >> PWM_STEP_SHIFT;
88 stride = PWM_MAX - stride;
109 void pwm_set(unsigned char n, uint16_t stride)
111 if (((stride + (1 << PWM_STEP_SHIFT)) >> PWM_STEP_SHIFT) >= PWM_MAX)
112 stride = PWM_MAX << PWM_STEP_SHIFT;
114 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
120 case 0: DDRB |= _BV(PB1); break;
121 case 1: DDRB |= _BV(PB3); break;
122 case 2: DDRB |= _BV(PB5); break;
131 if (++step >= (1 << PWM_STEP_SHIFT))
134 for (i = 0; i < N_PWMLEDS; i++)