SystemVerilog verification of VHDL design

Paper Abstract

This document describes digital design verification methods used in Liberouter project. Because of the high effort required for employing exhaustive formal verification method of model checking on large and rapidly developed designs, we have explored possibilities of supplementing this method by a relatively easily practicable simulation method based on the notion of testbenches. In particular, we report on SystemVerilog framework for automated and manageable tests and we highlight the most interesting aspects of both mentioned verification methods. Finally, we evaluate the SystemVerilog simulation on complex Internal Bus design. Very good results of SystemVerilog simulation encourage use of this approach to all critical and complex designs. We also state some preliminary ideas of how to combine both verification methods together to gain maximum of their features.

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