BENCHMARK INFORMATION benchmark definition: run_definitions/smtinterpol_inc_Equality+LinearArith.xml name: smtinterpol_inc_Equality+LinearArith run sets: SMTInterpol,1,Incremental.task date: Fri, 2025-06-27 00:35:15 CEST tool: SMTInterpol tool executable: ./unpack/b09520a1b066ea243f95b1ec64f83609eeb4c7819b7b9ff74d21aa3b718a7b92/smtinterpol options: property file: benchmarks/properties/SMT.prp resource limits: - memory: 8192.0 MB - time: 120 s - cpu cores: 2 hardware requirements: - cpu model: Intel Core i7 - cpu cores: 2 - memory: 8192.0 MB ------------------------------------------------------------ SMTInterpol,1,Incremental.task Run set 1 of 1 with options 'unpack/b09520a1b066ea243f95b1ec64f83609eeb4c7819b7b9ff74d21aa3b718a7b92/smtinterpol' and propertyfile 'benchmarks/properties/SMT.prp' inputfile status cpu time wall time host ------------------------------------------------------------------------------------------------------------------------------------------------------------------- UFLRA/UFLRA_asasp__empty_bench_3_3_7_empty.yml DONE (37 correct) 4.74 2.43 tc06 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_1_1_21_random3.yml DONE (24 correct) 3.45 1.79 tc05 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_1_1_6_random1.yml DONE (0 correct) 1.00 0.55 tc05 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_1_1_6_random8.yml DONE (0 correct) 0.88 0.48 tc03 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_2_2_17_random10.yml DONE (66 correct) 5.69 2.91 tc06 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_2_2_28_random5.yml DONE (0 correct) 1.11 0.61 tc08 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_3_3_10_random8.yml DONE (0 correct) 0.90 0.51 tc05 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_3_3_29_random9.yml DONE (0 correct) 1.10 0.60 tc02 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_4_4_21_random2.yml DONE (776 correct) 15.00 7.57 tc06 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_4_4_21_random9.yml DONE (168 correct) 5.46 2.79 tc05 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_4_4_29_random7.yml DONE (80 correct) 6.29 3.24 tc08 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_1_1_20_random1.yml TIMEOUT (TIMEOUT (1 correct)) 121.00 103.58 tc08 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_1_1_20_random8.yml TIMEOUT (TIMEOUT (0 correct)) 120.91 105.66 tc03 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_1_1_21_random2.yml TIMEOUT (TIMEOUT (0 correct)) 120.90 105.35 tc06 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_1_1_29_random2.yml TIMEOUT (TIMEOUT (0 correct)) 120.95 105.19 tc02 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_2_2_17_random1.yml TIMEOUT (TIMEOUT (1 correct)) 121.27 104.00 tc05 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_2_2_17_random8.yml TIMEOUT (TIMEOUT (0 correct)) 120.89 106.28 tc03 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_2_2_30_random9.yml TIMEOUT (TIMEOUT (0 correct)) 120.96 106.11 tc03 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_3_3_29_random1.yml TIMEOUT (TIMEOUT (0 correct)) 120.95 103.04 tc03 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_4_4_19_random7.yml TIMEOUT (TIMEOUT (0 correct)) 120.88 105.65 tc06 ALIA/ALIA_UltimateBuchiAutomizer_Ben-Amram-2010LMCS-Ex2.3-alloca_true-termination.c.i.yml DONE (7142 correct) 43.19 21.91 tc08 ALIA/ALIA_UltimateBuchiAutomizer_BrockschmidtCookFuhs-2013CAV-Fig1-alloca_true-termination.c.i.yml DONE (5752 correct) 33.79 17.00 tc08 ALIA/ALIA_UltimateBuchiAutomizer_CookSeeZuleger-2013TACAS-Fig7b-alloca_true-termination.c.i.yml DONE (7060 correct) 38.49 19.39 tc02 ALIA/ALIA_UltimateBuchiAutomizer_Urban-2013WST-Fig2-alloca_true-termination.c.i.yml TIMEOUT (DONE (13710 correct)) 85.55 61.13 tc03 ALIA/ALIA_UltimateBuchiAutomizer_a.04-alloca_true-termination.c.i.yml DONE (8090 correct) 43.74 23.07 tc05 ALIA/ALIA_UltimateBuchiAutomizer_a.08-alloca_true-termination.c.i.yml DONE (11540 correct) 54.07 27.41 tc05 ALIA/ALIA_UltimateBuchiAutomizer_a.09_assume-alloca_true-termination.c.i.yml DONE (8812 correct) 52.17 27.01 tc02 ALIA/ALIA_UltimateBuchiAutomizer_a.10-alloca_true-termination.c.i.yml DONE (8029 correct) 43.66 22.93 tc03 ALIA/ALIA_UltimateBuchiAutomizer_b.01-alloca_true-termination.c.i.yml DONE (7717 correct) 45.03 23.18 tc02 ALIA/ALIA_UltimateBuchiAutomizer_b.09-no-inv_assume-alloca_true-termination.c.i.yml DONE (8957 correct) 47.73 25.35 tc06 ALIA/ALIA_UltimateBuchiAutomizer_b.09_assume-alloca_true-termination.c.i.yml DONE (10287 correct) 51.58 27.40 tc05 ALIA/ALIA_UltimateBuchiAutomizer_b.11-alloca_true-termination.c.i.yml DONE (7927 correct) 46.45 24.23 tc03 ALIA/ALIA_UltimateBuchiAutomizer_b.16-alloca_true-termination.c.i.yml DONE (7986 correct) 43.38 22.93 tc06 ALIA/ALIA_UltimateBuchiAutomizer_c.01-no-inv-alloca_true-termination.c.i.yml DONE (7538 correct) 43.55 22.45 tc02 ALIA/ALIA_UltimateBuchiAutomizer_c.02-alloca_true-termination.c.i.yml DONE (7006 correct) 42.23 21.75 tc02 ALIA/ALIA_UltimateBuchiAutomizer_c.08-alloca_true-termination.c.i.yml DONE (6933 correct) 43.33 22.28 tc08 ALIA/ALIA_UltimateBuchiAutomizer_diff-alloca_true-termination.c.i.yml DONE (9775 correct) 55.94 33.12 tc06 ALIA/ALIA_UltimateBuchiAutomizer_java_AG313-alloca_true-termination.c.i.yml DONE (13967 correct) 69.47 45.76 tc08 ALIA/ALIA_UltimateBuchiAutomizer_lis-alloca_true-termination.c.i.yml DONE (6515 correct) 37.45 19.13 tc08 ALIA/ALIA_UltimateBuchiAutomizer_min_rf-alloca_true-termination.c.i.yml DONE (7007 correct) 41.79 20.99 tc02 ------------------------------------------------------------------------------------------------------------------------------------------------------------------- Run set 1 done None None - Statistics: 40 Files correct: 0 correct true: 0 correct false: 0 incorrect: 0 incorrect true: 0 incorrect false: 0 unknown: 40