BENCHMARK INFORMATION benchmark definition: run_definitions/cvc5_inc_Equality+LinearArith.xml name: cvc5_inc_Equality+LinearArith run sets: cvc5,3,Incremental.task date: Mon, 2025-06-23 14:56:08 CEST tool: cvc5 tool executable: ./unpack/1647fe1d9c9285ea0d2f2566270b82d066e64b381a008d32982da1d679391a6c/bin/starexec_run_sq options: property file: benchmarks/properties/SMT.prp resource limits: - memory: 8192.0 MB - time: 240 s - cpu cores: 2 hardware requirements: - cpu model: Intel Core i7 - cpu cores: 2 - memory: 8192.0 MB ------------------------------------------------------------ cvc5,3,Incremental.task Run set 1 of 1 with options 'unpack/5a2472e19477669429b98bad30984ceb59109d7a9f83532297e06bc8dfd2a949/bin/smtcomp_run_incremental' and propertyfile 'benchmarks/properties/SMT.prp' inputfile status cpu time wall time host ------------------------------------------------------------------------------------------------------------------------------------------------------------------- UFLRA/UFLRA_asasp__empty_bench_3_3_7_empty.yml DONE (37 correct) 0.96 0.96 tc03 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_1_1_21_random3.yml DONE (24 correct) 0.37 0.37 tc06 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_1_1_6_random1.yml DONE (0 correct) 0.03 0.03 tc02 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_1_1_6_random8.yml DONE (0 correct) 0.03 0.03 tc05 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_2_2_17_random10.yml DONE (66 correct) 0.81 0.80 tc02 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_2_2_28_random5.yml DONE (0 correct) 0.05 0.05 tc08 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_3_3_10_random8.yml DONE (0 correct) 0.04 0.04 tc03 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_3_3_29_random9.yml DONE (0 correct) 0.04 0.04 tc02 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_4_4_21_random2.yml DONE (776 correct) 3.14 3.13 tc06 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_4_4_21_random9.yml DONE (168 correct) 0.57 0.57 tc06 UFLRA/UFLRA_asasp__hierarchy_explicit_bench_4_4_29_random7.yml DONE (80 correct) 0.99 0.99 tc05 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_1_1_20_random1.yml DONE (14 correct) 0.79 0.79 tc06 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_1_1_20_random8.yml TIMEOUT (DONE (8 correct)) 60.75 60.75 tc05 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_1_1_21_random2.yml DONE (1 correct) 0.78 0.78 tc02 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_1_1_29_random2.yml DONE (7 correct) 1.76 1.76 tc05 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_2_2_17_random1.yml DONE (20 correct) 0.91 0.91 tc02 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_2_2_17_random8.yml TIMEOUT (TIMEOUT (9 correct)) 61.00 61.00 tc03 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_2_2_30_random9.yml TIMEOUT (TIMEOUT (8 correct)) 60.99 61.00 tc03 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_3_3_29_random1.yml DONE (0 correct) 0.08 0.08 tc03 UFLRA/UFLRA_asasp__hierarchy_implicit_bench_4_4_19_random7.yml TIMEOUT (TIMEOUT (13 correct)) 61.00 61.00 tc06 ALIA/ALIA_UltimateBuchiAutomizer_Ben-Amram-2010LMCS-Ex2.3-alloca_true-termination.c.i.yml DONE (7142 correct) 9.94 9.80 tc08 ALIA/ALIA_UltimateBuchiAutomizer_BrockschmidtCookFuhs-2013CAV-Fig1-alloca_true-termination.c.i.yml DONE (5755 correct) 6.88 6.77 tc08 ALIA/ALIA_UltimateBuchiAutomizer_CookSeeZuleger-2013TACAS-Fig7b-alloca_true-termination.c.i.yml DONE (7060 correct) 8.25 8.14 tc06 ALIA/ALIA_UltimateBuchiAutomizer_Urban-2013WST-Fig2-alloca_true-termination.c.i.yml DONE (13710 correct) 37.38 36.99 tc05 ALIA/ALIA_UltimateBuchiAutomizer_a.04-alloca_true-termination.c.i.yml DONE (8090 correct) 10.95 10.84 tc03 ALIA/ALIA_UltimateBuchiAutomizer_a.08-alloca_true-termination.c.i.yml DONE (11540 correct) 14.81 14.61 tc05 ALIA/ALIA_UltimateBuchiAutomizer_a.09_assume-alloca_true-termination.c.i.yml DONE (8812 correct) 14.08 13.88 tc08 ALIA/ALIA_UltimateBuchiAutomizer_a.10-alloca_true-termination.c.i.yml DONE (8029 correct) 10.94 10.77 tc08 ALIA/ALIA_UltimateBuchiAutomizer_b.01-alloca_true-termination.c.i.yml DONE (7717 correct) 10.38 10.24 tc02 ALIA/ALIA_UltimateBuchiAutomizer_b.09-no-inv_assume-alloca_true-termination.c.i.yml DONE (8968 correct) 13.22 13.07 tc06 ALIA/ALIA_UltimateBuchiAutomizer_b.09_assume-alloca_true-termination.c.i.yml DONE (10289 correct) 16.60 16.46 tc03 ALIA/ALIA_UltimateBuchiAutomizer_b.11-alloca_true-termination.c.i.yml DONE (7925 correct) 11.08 10.91 tc08 ALIA/ALIA_UltimateBuchiAutomizer_b.16-alloca_true-termination.c.i.yml DONE (7986 correct) 10.85 10.72 tc06 ALIA/ALIA_UltimateBuchiAutomizer_c.01-no-inv-alloca_true-termination.c.i.yml DONE (7538 correct) 9.99 9.85 tc08 ALIA/ALIA_UltimateBuchiAutomizer_c.02-alloca_true-termination.c.i.yml DONE (7009 correct) 9.53 9.37 tc02 ALIA/ALIA_UltimateBuchiAutomizer_c.08-alloca_true-termination.c.i.yml DONE (6933 correct) 9.63 9.48 tc05 ALIA/ALIA_UltimateBuchiAutomizer_diff-alloca_true-termination.c.i.yml DONE (9775 correct) 16.81 16.56 tc05 ALIA/ALIA_UltimateBuchiAutomizer_java_AG313-alloca_true-termination.c.i.yml DONE (13967 correct) 23.32 23.04 tc02 ALIA/ALIA_UltimateBuchiAutomizer_lis-alloca_true-termination.c.i.yml DONE (6515 correct) 9.02 8.88 tc08 ALIA/ALIA_UltimateBuchiAutomizer_min_rf-alloca_true-termination.c.i.yml DONE (7007 correct) 9.08 8.93 tc03 ------------------------------------------------------------------------------------------------------------------------------------------------------------------- Run set 1 done None 70.69 - Statistics: 40 Files correct: 0 correct true: 0 correct false: 0 incorrect: 0 incorrect true: 0 incorrect false: 0 unknown: 40