From 6d789ebc45563080cc731487a3a3455a3d8d6ef2 Mon Sep 17 00:00:00 2001 From: "Jan \"Yenya\" Kasprzak" Date: Mon, 25 Feb 2013 17:55:49 +0100 Subject: [PATCH] pcb: removed outline layer, bigger holes for USBASP --- tinyboard.pcb | 47 ++++++++++++++++++----------------------------- 1 file changed, 18 insertions(+), 29 deletions(-) diff --git a/tinyboard.pcb b/tinyboard.pcb index e37b03d..84a3753 100644 --- a/tinyboard.pcb +++ b/tinyboard.pcb @@ -6,12 +6,12 @@ FileVersion[20070407] PCB["" 200000 97500] Grid[500.0 0 0 0] -Cursor[14500 97500 0.000000] +Cursor[36000 9000 0.000000] PolyArea[200000000.000000] Thermal[0.500000] DRC[1000 1000 1000 1000 1500 1000] Flags("showdrc,nameonpcb,uniquename,clearnew,locknames") -Groups("1,c:2,s:3") +Groups("1,c:2,s") Styles["Signal,1000,4000,2000,1000:Power,2500,6000,3500,1000:Fat,6000,9000,5000,2000:Skinny,600,2402,1181,600"] Symbol[' ' 1800] @@ -1008,8 +1008,8 @@ Element["" "1206" "D1" "unknown" 125000 25000 -3150 -3150 0 100 ""] Element["" "RCY200" "L50" "unknown" 32500 55000 -12500 -4095 0 100 ""] ( - Pin[0 0 6000 3000 6600 3000 "1" "1" "square"] - Pin[-20000 0 6000 3000 6600 3000 "2" "2" ""] + Pin[0 0 6500 3000 7300 3500 "1" "1" "square"] + Pin[-20000 0 6500 3000 7300 3500 "2" "2" ""] ElementArc [-10000 0 20000 20000 180 360 1000] ) @@ -1347,16 +1347,16 @@ Element["" "JUMPER2" "J20" "unknown" 140000 25000 17500 -2500 0 100 ""] Element["" "HEADER10_1" "PROG" "unknown" 39500 15500 -20000 -12500 0 100 ""] ( - Pin[0 0 6000 3000 6600 3800 "1" "1" "square,edge2"] - Pin[10000 0 6000 3000 6600 3800 "2" "2" "edge2"] - Pin[20000 0 6000 3000 6600 3800 "3" "3" "edge2"] - Pin[30000 0 6000 3000 6600 3800 "4" "4" "edge2"] - Pin[40000 0 6000 3000 6600 3800 "5" "5" "edge2"] - Pin[40000 -10000 6000 3000 6600 3800 "6" "6" "edge2"] - Pin[30000 -10000 6000 3000 6600 3800 "7" "7" "edge2"] - Pin[20000 -10000 6000 3000 6600 3800 "8" "8" "edge2"] - Pin[10000 -10000 6000 3000 6600 3800 "9" "9" "edge2"] - Pin[0 -10000 6000 3000 6600 3800 "10" "10" "edge2"] + Pin[0 0 6800 3000 7600 3800 "1" "1" "square,edge2"] + Pin[10000 0 6800 3000 7600 3800 "2" "2" "edge2"] + Pin[20000 0 6800 3000 7600 3800 "3" "3" "edge2"] + Pin[30000 0 6800 3000 7600 3800 "4" "4" "edge2"] + Pin[40000 0 6800 3000 7600 3800 "5" "5" "edge2"] + Pin[40000 -10000 6800 3000 7600 3800 "6" "6" "edge2"] + Pin[30000 -10000 6800 3000 7600 3800 "7" "7" "edge2"] + Pin[20000 -10000 6800 3000 7600 3800 "8" "8" "edge2"] + Pin[10000 -10000 6800 3000 7600 3800 "9" "9" "edge2"] + Pin[0 -10000 6800 3000 7600 3800 "10" "10" "edge2"] ElementLine [-5000 5000 45000 5000 1000] ElementLine [45000 -15000 45000 5000 1000] ElementLine [-5000 -15000 45000 -15000 1000] @@ -1368,8 +1368,8 @@ Element["" "HEADER10_1" "PROG" "unknown" 39500 15500 -20000 -12500 0 100 ""] Element["" "RCY200" "L10" "unknown" 177500 25000 -3500 7000 0 100 ""] ( - Pin[0 0 6000 3000 6600 3000 "1" "1" "square"] - Pin[0 20000 6000 3000 6600 3000 "2" "2" ""] + Pin[0 0 6500 3000 7300 3500 "1" "1" "square"] + Pin[0 20000 6500 3000 7300 3500 "2" "2" ""] ElementArc [0 10000 20000 20000 270 360 1000] ) @@ -1688,18 +1688,7 @@ Layer(2 "solder") Line[132500 25000 132500 27500 1000 2000 "clearline"] Line[132500 27500 140000 35000 1000 2000 "clearline"] ) -Layer(3 "outline") -( - Line[10500 0 189500 0 1000 2000 "clearline"] - Line[200000 10500 200000 87000 1000 2000 "clearline"] - Line[0 10500 0 87000 1000 2000 "clearline"] - Line[189500 97500 10500 97500 1000 2000 "clearline"] - Arc[10500 10500 10500 10500 1000 2000 -90 90 "clearline"] - Arc[189500 10500 10500 10500 1000 2000 -90 -90 "clearline"] - Arc[189500 87000 10500 10500 1000 2000 180 -90 "clearline"] - Arc[10500 87000 10500 10500 1000 2000 0 90 "clearline"] -) -Layer(4 "silk") +Layer(3 "silk") ( Line[10500 97000 189500 97000 1000 2000 "clearline"] Line[199500 87000 199500 10500 1000 2000 "clearline"] @@ -1712,7 +1701,7 @@ Layer(4 "silk") Text[49800 25900 0 120 "Kasprzak" "clearline,onsolder"] Text[46800 33800 0 120 "Jan \"Yenya\"" "clearline,onsolder"] ) -Layer(5 "silk") +Layer(4 "silk") ( Line[137500 58500 136500 59500 1000 2000 "clearline"] Line[138000 58500 137500 58500 1000 2000 "clearline"] -- 2.39.3