/* output power and PWM calculation */
#define PWM_TOP 255
#define PWM_MAX (PWM_TOP - 8) // to allow for ADC "batt_off" measurements
+#define PWM_MIN 8 // to allow for ADC "batt_on" measurements
/*
* The values in power_levels[] array are voltages at which the load
PORTB &= ~_BV(PB4);
// TCCR1 = _BV(CS10); // clk/1 = 1 MHz
- TCCR1 = _BV(CS11) | _BV(CS13); // clk/512 = 2 kHz
+ // TCCR1 = _BV(CS11) | _BV(CS13); // clk/512 = 2 kHz
+ /*
+ * clk/64 = 16 kHz. We use PWM_MIN and PWM_MAX, so we have at least
+ * 8 full T/C1 cycles to do two ADC measurements. The ADC with 125 kHz
+ * clock can do about 7000-9000 measurement per second, so we should
+ * be safe both on low and high OCR1B values with this clock
+ */
+ TCCR1 = _BV(CS12) | _BV(CS11) | _BV(CS10);
+
GTCCR = _BV(COM1B1) | _BV(PWM1B);
OCR1C = PWM_TOP;
// OCR1B = steps[0];
ISR(TIM1_OVF_vect)
{
- adc_drop = 2;
+ adc_drop = 1;
adc_type = 1;
adc_start_measurement();
}
ISR(TIM1_COMPB_vect)
{
- adc_drop = 2;
+ adc_drop = 1;
adc_type = 0;
adc_start_measurement();
}
if (pwm > PWM_MAX)
pwm = PWM_MAX;
+ if (pwm < PWM_MIN)
+ pwm = PWM_MIN;
+
log_byte(0x10 + power_level);
log_byte(batt_on8);
log_byte(pwm & 0xFF);