2 C 40000 40000 0 0 0 title-B.sym
3 C 47700 44600 1 90 0 zener-1.sym
5 T 47100 45000 5 10 0 0 90 0 1
7 T 47200 44900 5 10 1 1 90 0 1
9 T 47900 44900 5 10 1 1 90 0 1
12 C 47600 45900 1 90 0 resistor-2.sym
14 T 47250 46300 5 10 0 0 90 0 1
16 T 47300 46100 5 10 1 1 90 0 1
18 T 47900 46100 5 10 1 1 90 0 1
21 N 47500 46800 47500 47000 4
22 N 47500 47000 48500 47000 4
23 N 47500 44600 47500 44400 4
24 N 45500 44400 48500 44400 4
25 N 47500 45900 47500 45500 4
26 N 47500 45700 45500 45700 4
27 C 45500 45800 1 180 0 output-1.sym
29 T 45400 45500 5 10 0 0 180 0 1
31 T 44700 45400 5 10 1 1 0 0 1
32 pinlabel=Data pin (e.g.D2 on Nano)
34 C 45500 44500 1 180 0 output-1.sym
36 T 45400 44200 5 10 0 0 180 0 1
38 T 44700 44600 5 10 1 1 0 0 1
41 C 49300 47100 1 180 0 input-1.sym
43 T 49300 46800 5 10 0 0 180 0 1
45 T 48300 46700 5 10 1 1 0 0 1
46 pinlabel=Right rail (+18V)
48 C 49300 44500 1 180 0 input-1.sym
50 T 49300 44200 5 10 0 0 180 0 1
52 T 48300 44600 5 10 1 1 0 0 1
53 pinlabel=Left rail (GND)
55 T 48300 45700 9 10 1 0 0 0 1
57 T 44700 45000 9 10 1 0 0 0 1