Paper Details

Formal Verification Framework and Applications for the Massive Usage at Intel
Zyiad Hanna

The continuous development and innovations of formal verification technologies during the last decade; put lots of hope and significantly raised the confidence level of the Industrial design teams to apply formal methods for improving the overall chip design verification cycle. In particular, we at Intel have been developing formal verification technologies and tools and employing them for the benefits of the majority of Pentium and Itanium projects. In this talk, I will present our experience in this domain, the usage model, overview our Intel Formal verification framework (FORTE), and discuss the major applications (FEV, FPV) for verifying the design correctness and design implementation. During the talk, I will convey the main challenges and the future of formal verification that we see at Intel.