commit bb2bdf38b8b02176888cd3b8cea25fd44dffae68
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Mon Aug 27 10:29:24 2007 +0200

    convert many retval bools to ints

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 3e1d85b..ccd5b9b 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -61,6 +61,9 @@ static int ath5k_hw_get_capabilities(struct ath_hw *);
 static int ath5k_eeprom_init(struct ath_hw *);
 static int ath5k_eeprom_read_mac(struct ath_hw *, u8 *);
 
+static int ath5k_hw_enable_pspoll(struct ath_hw *, u8 *, u16);
+static int ath5k_hw_disable_pspoll(struct ath_hw *);
+
 /*
  * Enable to overwrite the country code (use "00" for debug)
  */
@@ -1265,8 +1268,7 @@ int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue)
  * Stop DMA transmit for a specific queue
  * (see also QCU/DCU functions)
  */
-bool
-ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue)
+int ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue)
 {
 	unsigned int i = 100;
 	u32 tx_queue, pending;
@@ -1276,7 +1278,7 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue)
 
 	/* Return if queue is declared inactive */
 	if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
-		return false;
+		return -EIO;
 
 	if (hal->ah_version == AR5K_AR5210) {
 		tx_queue = ath5k_hw_reg_read(hal, AR5K_CR);
@@ -1295,7 +1297,7 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue)
 			ath5k_hw_reg_write(hal, 0, AR5K_BSR);
 			break;
 		default:
-			return false;
+			return -EINVAL;
 		}
 
 		/* Stop queue */
@@ -1318,8 +1320,8 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue)
 		ath5k_hw_reg_write(hal, 0, AR5K_QCU_TXD);
 	}
 
-	/* TODO: Check for success else return false */
-	return true;
+	/* TODO: Check for success else return error */
+	return 0;
 }
 
 /*
@@ -1404,11 +1406,10 @@ int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr)
 /*
  * Update tx trigger level
  */
-bool
-ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase)
+int ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase)
 {
 	u32 trigger_level, imr;
-	bool status = false;
+	int ret = -EIO;
 
 	AR5K_TRACE;
 
@@ -1437,7 +1438,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase)
 		AR5K_REG_WRITE_BITS(hal, AR5K_TXCFG,
 				AR5K_TXCFG_TXFULL, trigger_level);
 
-	status = true;
+	ret = 0;
 
 done:
 	/*
@@ -1445,7 +1446,7 @@ done:
 	 */
 	ath5k_hw_set_intr(hal, imr);
 
-	return status;
+	return ret;
 }
 
 /*
@@ -2252,8 +2253,7 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal)
 /*
  * Set Operation mode
  */
-void
-ath5k_hw_set_opmode(struct ath_hw *hal)
+int ath5k_hw_set_opmode(struct ath_hw *hal)
 {
 	u32 pcu_reg, beacon_reg, low_id, high_id;
 
@@ -2288,7 +2288,7 @@ ath5k_hw_set_opmode(struct ath_hw *hal)
 		break;
 
 	default:
-		return;
+		return -EINVAL;
 	}
 
 	/*
@@ -2304,6 +2304,8 @@ ath5k_hw_set_opmode(struct ath_hw *hal)
 	 */
 	if (hal->ah_version == AR5K_AR5210)
 		ath5k_hw_reg_write(hal, beacon_reg, AR5K_BCR);
+
+	return 0;
 }
 
 /*
@@ -2322,8 +2324,7 @@ void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac)
 /*
  * Set station id
  */
-bool
-ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac)
+int ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac)
 {
 	u32 low_id, high_id;
 
@@ -2337,14 +2338,13 @@ ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac)
 	ath5k_hw_reg_write(hal, low_id, AR5K_STA_ID0);
 	ath5k_hw_reg_write(hal, high_id, AR5K_STA_ID1);
 
-	return true;
+	return 0;
 }
 
 /*
  * Set BSSID
  */
-void
-ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id)
+void ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id)
 {
 	u32 low_id, high_id;
 	u16 tim_offset = 0;
@@ -2381,8 +2381,7 @@ ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id)
 /*
  * Set BSSID mask on 5212
  */
-bool
-ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8 *mask)
+int ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8 *mask)
 {
 	u32 low_id, high_id;
 	AR5K_TRACE;
@@ -2394,10 +2393,10 @@ ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8 *mask)
 		ath5k_hw_reg_write(hal, low_id, AR5K_BSS_IDM0);
 		ath5k_hw_reg_write(hal, high_id, AR5K_BSS_IDM1);
 
-		return true;
+		return 0;
 	}
 
-	return false;
+	return -EIO;
 }
 
 /*
@@ -2407,8 +2406,7 @@ ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8 *mask)
 /*
  * Start receive on PCU
  */
-void
-ath5k_hw_start_rx_pcu(struct ath_hw *hal)
+void ath5k_hw_start_rx_pcu(struct ath_hw *hal)
 {
 	AR5K_TRACE;
 	AR5K_REG_DISABLE_BITS(hal, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
@@ -2417,8 +2415,7 @@ ath5k_hw_start_rx_pcu(struct ath_hw *hal)
 /*
  * Stop receive on PCU
  */
-void
-ath5k_hw_stop_pcu_recv(struct ath_hw *hal)
+void ath5k_hw_stop_pcu_recv(struct ath_hw *hal)
 {
 	AR5K_TRACE;
 	AR5K_REG_ENABLE_BITS(hal, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
@@ -2431,8 +2428,7 @@ ath5k_hw_stop_pcu_recv(struct ath_hw *hal)
 /*
  * Set multicast filter
  */
-void
-ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, u32 filter1)
+void ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, u32 filter1)
 {
 	AR5K_TRACE;
 	/* Set the multicat filter */
@@ -2443,46 +2439,43 @@ ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, u32 filter1)
 /*
  * Set multicast filter by index
  */
-bool
-ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index)
+int ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index)
 {
 
 	AR5K_TRACE;
 	if (index >= 64)
-		return false;
+		return -EINVAL;
 	else if (index >= 32)
 		AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER1,
 				(1 << (index - 32)));
 	else
 		AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER0, (1 << index));
 
-	return true;
+	return 0;
 }
 
 /*
  * Clear Multicast filter by index
  */
-bool
-ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index)
+int ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index)
 {
 
 	AR5K_TRACE;
 	if (index >= 64)
-		return false;
+		return -EINVAL;
 	else if (index >= 32)
 		AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER1,
 				(1 << (index - 32)));
 	else
 		AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER0, (1 << index));
 
-	return true;
+	return 0;
 }
 
 /*
  * Get current rx filter
  */
-u32
-ath5k_hw_get_rx_filter(struct ath_hw *ah)
+u32 ath5k_hw_get_rx_filter(struct ath_hw *ah)
 {
 	u32 data, filter = 0;
 
@@ -2624,8 +2617,7 @@ void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32 interval)
 /*
  * Set beacon timers
  */
-void
-ath5k_hw_set_beacon_timers(struct ath_hw *hal,
+int ath5k_hw_set_beacon_timers(struct ath_hw *hal,
 		const struct ath5k_beacon_state *state)
 {
 	u32 cfp_period, next_cfp, dtim, interval, next_beacon;
@@ -2645,7 +2637,7 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal,
 	AR5K_TRACE;
 	/* Return on an invalid beacon state */
 	if (state->bs_interval < 1)
-		return;
+		return -EINVAL;
 
 	interval = state->bs_interval;
 	dtim = state->bs_dtim_period;
@@ -2725,7 +2717,7 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal,
 			dtim = state->bs_sleep_duration;
 
 		if (interval > dtim)
-			return;
+			return -EINVAL;
 
 		next_beacon = interval == dtim ? state->bs_next_dtim :
 			state->bs_next_beacon;
@@ -2745,13 +2737,14 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal,
 			AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) |
 			AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2);
 	}
+
+	return 0;
 }
 
 /*
  * Reset beacon timers
  */
-void
-ath5k_hw_reset_beacon(struct ath_hw *hal)
+void ath5k_hw_reset_beacon(struct ath_hw *hal)
 {
 	AR5K_TRACE;
 	/*
@@ -2771,11 +2764,10 @@ ath5k_hw_reset_beacon(struct ath_hw *hal)
  * Wait for beacon queue to finish
  * TODO: This function's name is misleading, rename
  */
-bool
-ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr)
+int ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr)
 {
 	unsigned int i;
-	bool ret;
+	int ret;
 
 	AR5K_TRACE;
 
@@ -2802,17 +2794,17 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr)
 			ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
 					AR5K_BCR);
 
-			return false;
+			return -EIO;
 		}
-		ret = true;
+		ret = 0;
 	} else {
 	/*5211/5212*/
 		ret = ath5k_hw_register_timeout(hal,
 			AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON),
-			AR5K_QCU_STS_FRMPENDCNT, 0, false) ? false : true;
+			AR5K_QCU_STS_FRMPENDCNT, 0, false);
 
 		if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON))
-			return false;
+			return -EIO;
 	}
 
 	return ret;
@@ -2821,8 +2813,7 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr)
 /*
  * Update mib counters (statistics)
  */
-void
-ath5k_hw_update_mib_counters(struct ath_hw *hal,
+void ath5k_hw_update_mib_counters(struct ath_hw *hal,
 		struct ath5k_mib_stats *statistics)
 {
 	AR5K_TRACE;
@@ -2849,58 +2840,54 @@ ath5k_hw_update_mib_counters(struct ath_hw *hal,
 /*
  * Set ACK timeout on PCU
  */
-bool
-ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout)
+int ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout)
 {
 	AR5K_TRACE;
 	if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK),
 			hal->ah_turbo) <= timeout)
-		return false;
+		return -EINVAL;
 
 	AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
 		ath5k_hw_htoclock(timeout, hal->ah_turbo));
 
-	return true;
+	return 0;
 }
 
 /*
  * Read the ACK timeout from PCU
  */
-unsigned int
-ath5k_hw_get_ack_timeout(struct ath_hw *hal)
+unsigned int ath5k_hw_get_ack_timeout(struct ath_hw *hal)
 {
 	AR5K_TRACE;
 
-	return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal,
-			AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), hal->ah_turbo));
+	return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal,
+			AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), hal->ah_turbo);
 }
 
 /*
  * Set CTS timeout on PCU
  */
-bool
-ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout)
+int ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout)
 {
 	AR5K_TRACE;
 	if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS),
 			hal->ah_turbo) <= timeout)
-		return false;
+		return -EINVAL;
 
 	AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
 			ath5k_hw_htoclock(timeout, hal->ah_turbo));
 
-	return true;
+	return 0;
 }
 
 /*
  * Read CTS timeout from PCU
  */
-unsigned int
-ath5k_hw_get_cts_timeout(struct ath_hw *hal)
+unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal)
 {
 	AR5K_TRACE;
-	return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal,
-			AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), hal->ah_turbo));
+	return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal,
+			AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), hal->ah_turbo);
 }
 
 /*
@@ -3388,8 +3375,7 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
  * Get number of pending frames
  * for a specific queue [5211+]
  */
-u32
-ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue) {
+u32 ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue) {
 	AR5K_TRACE;
 	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
 
@@ -3407,12 +3393,11 @@ ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue) {
 /*
  * Set slot time
  */
-bool
-ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time)
+int ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time)
 {
 	AR5K_TRACE;
 	if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX)
-		return false;
+		return -EINVAL;
 
 	if (hal->ah_version == AR5K_AR5210)
 		ath5k_hw_reg_write(hal, ath5k_hw_htoclock(slot_time,
@@ -3420,19 +3405,18 @@ ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time)
 	else
 		ath5k_hw_reg_write(hal, slot_time, AR5K_DCU_GBL_IFS_SLOT);
 
-	return true;
+	return 0;
 }
 
 /*
  * Get slot time
  */
-unsigned int
-ath5k_hw_get_slot_time(struct ath_hw *hal)
+unsigned int ath5k_hw_get_slot_time(struct ath_hw *hal)
 {
 	AR5K_TRACE;
 	if (hal->ah_version == AR5K_AR5210)
-		return (ath5k_hw_clocktoh(ath5k_hw_reg_read(hal,
-				AR5K_SLOT_TIME) & 0xffff, hal->ah_turbo));
+		return ath5k_hw_clocktoh(ath5k_hw_reg_read(hal,
+				AR5K_SLOT_TIME) & 0xffff, hal->ah_turbo);
 	else
 		return ath5k_hw_reg_read(hal, AR5K_DCU_GBL_IFS_SLOT) & 0xffff;
 }
@@ -4358,38 +4342,41 @@ yes:
 	return 0;
 }
 
-bool
-ath5k_hw_query_pspoll_support(struct ath_hw *hal)
+#if 0
+static bool ath5k_hw_query_pspoll_support(struct ath_hw *hal)
 {
 	AR5K_TRACE;
+
 	if (hal->ah_version == AR5K_AR5210)
-		return(true);
+		return true;
 
 	return false;
 }
+#endif
 
-bool
-ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id)
+static int ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid,
+		u16 assoc_id)
 {
 	AR5K_TRACE;
+
 	if (hal->ah_version == AR5K_AR5210) {
 		AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1,
 			AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
-		return true;
+		return 0;
 	}
 
-	return false;
+	return -EIO;
 }
 
-bool
-ath5k_hw_disable_pspoll(struct ath_hw *hal)
+static int ath5k_hw_disable_pspoll(struct ath_hw *hal)
 {
 	AR5K_TRACE;
+
 	if (hal->ah_version == AR5K_AR5210) {
 		AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1,
 			AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
-		return true;
+		return 0;
 	}
 
-	return false;
+	return -EIO;
 }

commit bb7405eef9dc9bcbd2eb6ace5e3fcb06d4061320
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Mon Aug 27 10:11:10 2007 +0200

    split hw into hw, phy and initvals

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 47fc6f2..3e1d85b 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -37,8 +37,6 @@ static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR;
 /*Prototypes*/
 static int ath5k_hw_nic_reset(struct ath_hw *, u32);
 static int ath5k_hw_nic_wakeup(struct ath_hw *, int, bool);
-static u16 ath5k_hw_radio_revision(struct ath_hw *, unsigned int);
-static int ath5k_hw_txpower(struct ath_hw *, struct ieee80211_channel *, unsigned int);
 static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *, struct ath_desc *,
 	unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
 	unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
@@ -63,51 +61,6 @@ static int ath5k_hw_get_capabilities(struct ath_hw *);
 static int ath5k_eeprom_init(struct ath_hw *);
 static int ath5k_eeprom_read_mac(struct ath_hw *, u8 *);
 
-static int ath5k_hw_channel(struct ath_hw *, struct ieee80211_channel *);
-static int ath5k_hw_rfregs(struct ath_hw *, struct ieee80211_channel *,
-		unsigned int);
-static int ath5k_hw_rf5111_rfregs(struct ath_hw *, struct ieee80211_channel *,
-		unsigned int);
-static int ath5k_hw_rf5112_rfregs(struct ath_hw *, struct ieee80211_channel *,
-		unsigned int);
-static int ath5k_hw_rfgain(struct ath_hw *, unsigned int);
-
-/*
- * Initial register dumps
- */
-
-/*
- * MAC/PHY Settings
- */
-/* Common for all modes */
-static const struct ath5k_ini ar5210_ini[] = AR5K_AR5210_INI;
-static const struct ath5k_ini ar5211_ini[] = AR5K_AR5211_INI;
-static const struct ath5k_ini ar5212_ini[] = AR5K_AR5212_INI;
-
-/* Mode-specific settings */
-static const struct ath5k_ini_mode ar5211_ini_mode[] = AR5K_AR5211_INI_MODE;
-static const struct ath5k_ini_mode ar5212_ini_mode[] = AR5K_AR5212_INI_MODE;
-static const struct ath5k_ini_mode ar5212_rf5111_ini_mode[] = AR5K_AR5212_RF5111_INI_MODE;
-static const struct ath5k_ini_mode ar5212_rf5112_ini_mode[] = AR5K_AR5212_RF5112_INI_MODE;
-
-/* RF Initial BB gain settings */
-static const struct ath5k_ini rf5111_ini_bbgain[] = AR5K_RF5111_INI_BBGAIN;
-static const struct ath5k_ini rf5112_ini_bbgain[] = AR5K_RF5112_INI_BBGAIN;
-
-/*
- * RF Settings
- */
-/* RF Banks */
-static const struct ath5k_ini_rf rf5111_rf[] = AR5K_RF5111_INI_RF;
-static const struct ath5k_ini_rf rf5112_rf[] = AR5K_RF5112_INI_RF;
-static const struct ath5k_ini_rf rf5112a_rf[] = AR5K_RF5112A_INI_RF;
-/* Initial mode-specific RF gain table for 5111/5112 */
-static const struct ath5k_ini_rfgain rf5111_ini_rfgain[] = AR5K_RF5111_INI_RFGAIN;
-static const struct ath5k_ini_rfgain rf5112_ini_rfgain[] = AR5K_RF5112_INI_RFGAIN;
-/* Initial gain optimization tables */
-static const struct ath5k_gain_opt rf5111_gain_opt = AR5K_RF5111_GAIN_OPT;
-static const struct ath5k_gain_opt rf5112_gain_opt = AR5K_RF5112_GAIN_OPT;
-
 /*
  * Enable to overwrite the country code (use "00" for debug)
  */
@@ -191,19 +144,6 @@ ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates,
  * Functions used internaly
  */
 
-static u32
-ath5k_hw_bitswap(u32 val, unsigned int bits)
-{
-	u32 retval = 0, bit, i;
-
-	for (i = 0; i < bits; i++) {
-		bit = (val >> i) & 1;
-		retval = (retval << 1) | bit;
-	}
-
-	return retval;
-}
-
 static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
 {
 	return turbo == true ? (usec * 80) : (usec * 40);
@@ -215,26 +155,10 @@ static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
 }
 
 /*
- * Read from a device register
- */
-static inline u32 ath5k_hw_reg_read(struct ath_hw *hal, u16 reg)
-{
-	return readl(hal->ah_sh + reg);
-}
-
-/*
- * Write to a device register
- */
-static inline void ath5k_hw_reg_write(struct ath_hw *hal, u32 val, u16 reg)
-{
-	writel(val, hal->ah_sh + reg);
-}
-
-/*
  * Check if a register write has been completed
  */
-static int ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag,
-		u32 val, bool is_set)
+int ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, u32 val,
+		bool is_set)
 {
 	int i;
 	u32 data;
@@ -251,50 +175,6 @@ static int ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag,
 	return (i <= 0) ? -EAGAIN : 0;
 }
 
-/*
- * Write initial register dump
- */
-static void ath5k_hw_ini_registers(struct ath_hw *hal, unsigned int size,
-		const struct ath5k_ini *ini_regs, bool change_channel)
-{
-	unsigned int i;
-
-	/* Write initial registers */
-	for (i = 0; i < size; i++) {
-		/* On channel change there is
-		 * no need to mess with PCU */
-		if (change_channel &&
-				ini_regs[i].ini_register >= AR5K_PCU_MIN &&
-				ini_regs[i].ini_register <= AR5K_PCU_MAX)
-			continue;
-
-		switch (ini_regs[i].ini_mode) {
-		case AR5K_INI_READ:
-			/* Cleared on read */
-			ath5k_hw_reg_read(hal, ini_regs[i].ini_register);
-			break;
-		case AR5K_INI_WRITE:
-		default:
-			AR5K_REG_WAIT(i);
-			ath5k_hw_reg_write(hal, ini_regs[i].ini_value,
-					ini_regs[i].ini_register);
-		}
-	}
-}
-
-static void ath5k_hw_ini_mode_registers(struct ath_hw *hal,
-		unsigned int size, const struct ath5k_ini_mode *ini_mode,
-		u8 mode)
-{
-	unsigned int i;
-
-	for (i = 0; i < size; i++) {
-		AR5K_REG_WAIT(i);
-		ath5k_hw_reg_write(hal, ini_mode[i].mode_value[mode],
-			(u32)ini_mode[i].mode_register);
-	}
-
-}
 
 /***************************************\
 	Attach/Detach Functions
@@ -462,24 +342,7 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc,
 
 	ath5k_hw_set_lladdr(hal, mac);
 
-	/* Initialize the gain optimization values */
-	/*For RF5111*/
-	if (hal->ah_radio == AR5K_RF5111) {
-		hal->ah_gain.g_step_idx = rf5111_gain_opt.go_default;
-		hal->ah_gain.g_step =
-		    &rf5111_gain_opt.go_step[hal->ah_gain.g_step_idx];
-		hal->ah_gain.g_low = 20;
-		hal->ah_gain.g_high = 35;
-		hal->ah_gain.g_active = 1;
-	/*For RF5112*/
-	} else if (hal->ah_radio == AR5K_RF5112) {
-		hal->ah_gain.g_step_idx = rf5112_gain_opt.go_default;
-		hal->ah_gain.g_step =
-		    &rf5111_gain_opt.go_step[hal->ah_gain.g_step_idx];
-		hal->ah_gain.g_low = 20;
-		hal->ah_gain.g_high = 85;
-		hal->ah_gain.g_active = 1;
-	}
+	ath5k_hw_set_rfgain_opt(hal);
 
 	return hal;
 err_free:
@@ -621,54 +484,6 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial)
 }
 
 /*
- * Get the PHY Chip revision
- */
-static u16 ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan)
-{
-	unsigned int i;
-	u32 srev;
-	u16 ret;
-
-	AR5K_TRACE;
-
-	/*
-	 * Set the radio chip access register
-	 */
-	switch (chan) {
-	case CHANNEL_2GHZ:
-		ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
-		break;
-	case CHANNEL_5GHZ:
-		ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
-		break;
-	default:
-		return 0;
-	}
-
-	mdelay(2);
-
-	/* ...wait until PHY is ready and read the selected radio revision */
-	ath5k_hw_reg_write(hal, 0x00001c16, AR5K_PHY(0x34));
-
-	for (i = 0; i < 8; i++)
-		ath5k_hw_reg_write(hal, 0x00010000, AR5K_PHY(0x20));
-
-	if (hal->ah_version == AR5K_AR5210) {
-		srev = ath5k_hw_reg_read(hal, AR5K_PHY(256) >> 28) & 0xf;
-		ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
-	} else {
-		srev = (ath5k_hw_reg_read(hal, AR5K_PHY(0x100)) >> 24) & 0xff;
-		ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
-				((srev & 0x0f) << 4), 8);
-	}
-
-	/* Reset to the 5GHz mode */
-	ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
-
-	return ret;
-}
-
-/*
  * Get the rate table for a specific operation mode
  */
 const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal,
@@ -826,60 +641,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 
 	}
 
-	/*
-	 * Write initial mode-specific settings
-	 */
-	/*For 5212*/
-	if (hal->ah_version == AR5K_AR5212) {
-		ath5k_hw_ini_mode_registers(hal, ARRAY_SIZE(ar5212_ini_mode),
-				ar5212_ini_mode, mode);
-		if (hal->ah_radio == AR5K_RF5111)
-			ath5k_hw_ini_mode_registers(hal,
-					ARRAY_SIZE(ar5212_rf5111_ini_mode),
-					ar5212_rf5111_ini_mode, mode);
-		else if (hal->ah_radio == AR5K_RF5112)
-			ath5k_hw_ini_mode_registers(hal,
-					ARRAY_SIZE(ar5212_rf5112_ini_mode),
-					ar5212_rf5112_ini_mode, mode);
-	}
-	/*For 5211*/
-	if (hal->ah_version == AR5K_AR5211)
-		ath5k_hw_ini_mode_registers(hal, ARRAY_SIZE(ar5211_ini_mode),
-				ar5211_ini_mode, mode);
-	/* For 5210 mode settings check out ath5k_hw_reset_tx_queue */
-
-	/*
-	 * Write initial settings common for all modes
-	 */
-	/*For 5212*/
-	if (hal->ah_version == AR5K_AR5212) {
-		ath5k_hw_ini_registers(hal, ARRAY_SIZE(ar5212_ini),
-				ar5212_ini, change_channel);
-		if (hal->ah_radio == AR5K_RF5112) {
-			ath5k_hw_reg_write(hal, AR5K_PHY_PAPD_PROBE_INI_5112,
-					AR5K_PHY_PAPD_PROBE);
-			ath5k_hw_ini_registers(hal,
-					ARRAY_SIZE(rf5112_ini_bbgain),
-					rf5112_ini_bbgain, change_channel);
-		} else if (hal->ah_radio == AR5K_RF5111) {
-			ath5k_hw_reg_write(hal, AR5K_PHY_GAIN_2GHZ_INI_5111,
-					AR5K_PHY_GAIN_2GHZ);
-			ath5k_hw_reg_write(hal, AR5K_PHY_PAPD_PROBE_INI_5111,
-					AR5K_PHY_PAPD_PROBE);
-			ath5k_hw_ini_registers(hal,
-					ARRAY_SIZE(rf5111_ini_bbgain),
-					rf5111_ini_bbgain, change_channel);
-		}
-	} else if (hal->ah_version == AR5K_AR5211) {
-		ath5k_hw_ini_registers(hal, ARRAY_SIZE(ar5211_ini),
-				ar5211_ini, change_channel);
-		/* AR5211 only comes with 5111 */
-		ath5k_hw_ini_registers(hal, ARRAY_SIZE(rf5111_ini_bbgain),
-				rf5111_ini_bbgain, change_channel);
-	} else if (hal->ah_version == AR5K_AR5210) {
-		ath5k_hw_ini_registers(hal, ARRAY_SIZE(ar5210_ini),
-				ar5210_ini, change_channel);
-	}
+	ath5k_hw_write_initvals(hal, mode, change_channel);
 
 	/*
 	 * 5211/5212 Specific
@@ -1373,6 +1135,7 @@ commit:
 	return 0;
 }
 
+#if 0
 /*
  * Get power mode (sleep state)
  * TODO:Remove ?
@@ -1383,7 +1146,7 @@ ath5k_hw_get_power_mode(struct ath_hw *hal)
 	AR5K_TRACE;
 	return hal->ah_power_mode;
 }
-
+#endif
 
 /***********************\
   DMA Related Functions
@@ -1814,6 +1577,7 @@ enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask)
 	return old_mask;
 }
 
+#if 0
 /*
  * Enable HW radar detection
  */
@@ -1856,7 +1620,7 @@ ath5k_hw_radar_alert(struct ath_hw *hal, bool enable)
 	/*Re-enable interrupts*/
 	ath5k_hw_reg_write(hal, AR5K_IER_ENABLE, AR5K_IER);
 }
-
+#endif
 
 
 
@@ -4417,24 +4181,6 @@ void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio,
  Regulatory Domain/Channels Setup
 \*********************************/
 
-/*
- * Check if a channel is supported
- */
-bool ath5k_channel_ok(struct ath_hw *hal, u16 freq, unsigned int flags)
-{
-	/* Check if the channel is in our supported range */
-	if (flags & CHANNEL_2GHZ) {
-		if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) &&
-		    (freq <= hal->ah_capabilities.cap_range.range_2ghz_max))
-			return true;
-	} else if (flags & CHANNEL_5GHZ)
-		if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) &&
-		    (freq <= hal->ah_capabilities.cap_range.range_5ghz_max))
-			return true;
-
-	return false;
-}
-
 u16 ath5k_get_regdomain(struct ath_hw *hal)
 {
 	u16 regdomain;
@@ -4461,1042 +4207,6 @@ u16 ath5k_get_regdomain(struct ath_hw *hal)
 	return regdomain;
 }
 
-/*************************\
-  PHY/RF access functions
-\*************************/
-
-/*
- * Convertion needed for RF5110
- */
-static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
-{
-	u32 athchan;
-
-	/*
-	 * Convert IEEE channel/MHz to an internal channel value used
-	 * by the AR5210 chipset. This has not been verified with
-	 * newer chipsets like the AR5212A who have a completely
-	 * different RF/PHY part.
-	 */
-	athchan = (ath5k_hw_bitswap((channel->chan - 24) / 2, 5) << 1) |
-		(1 << 6) | 0x1;
-
-	return athchan;
-}
-
-/*
- * Set channel on RF5110
- */
-static int ath5k_hw_rf5110_channel(struct ath_hw *hal,
-		struct ieee80211_channel *channel)
-{
-	u32 data;
-
-	/*
-	 * Set the channel and wait
-	 */
-	data = ath5k_hw_rf5110_chan2athchan(channel);
-	ath5k_hw_reg_write(hal, data, AR5K_RF_BUFFER);
-	ath5k_hw_reg_write(hal, 0, AR5K_RF_BUFFER_CONTROL_0);
-	mdelay(1);
-
-	return 0;
-}
-
-/*
- * Convertion needed for 5111
- */
-static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
-		struct ath5k_athchan_2ghz *athchan)
-{
-	int channel;
-
-	/* Cast this value to catch negative channel numbers (>= -19) */
-	channel = (int)ieee;
-
-	/*
-	 * Map 2GHz IEEE channel to 5GHz Atheros channel
-	 */
-	if (channel <= 13) {
-		athchan->a2_athchan = 115 + channel;
-		athchan->a2_flags = 0x46;
-	} else if (channel == 14) {
-		athchan->a2_athchan = 124;
-		athchan->a2_flags = 0x44;
-	} else if (channel >= 15 && channel <= 26) {
-		athchan->a2_athchan = ((channel - 14) * 4) + 132;
-		athchan->a2_flags = 0x46;
-	} else
-		return -EINVAL;
-
-	return 0;
-}
-
-/*
- * Set channel on 5111
- */
-static int ath5k_hw_rf5111_channel(struct ath_hw *hal,
-		struct ieee80211_channel *channel)
-{
-	struct ath5k_athchan_2ghz ath_channel_2ghz;
-	unsigned int ath_channel = channel->chan;
-	u32 data0, data1, clock;
-	int ret;
-
-	/*
-	 * Set the channel on the RF5111 radio
-	 */
-	data0 = data1 = 0;
-
-	if (channel->val & CHANNEL_2GHZ) {
-		/* Map 2GHz channel to 5GHz Atheros channel ID */
-		ret = ath5k_hw_rf5111_chan2athchan(channel->chan,
-				&ath_channel_2ghz);
-		if (ret)
-			return ret;
-
-		ath_channel = ath_channel_2ghz.a2_athchan;
-		data0 = ((ath5k_hw_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff)
-		    << 5) | (1 << 4);
-	}
-
-	if (ath_channel < 145 || !(ath_channel & 1)) {
-		clock = 1;
-		data1 = ((ath5k_hw_bitswap(ath_channel - 24, 8) & 0xff) << 2) |
-			(clock << 1) | (1 << 10) | 1;
-	} else {
-		clock = 0;
-		data1 = ((ath5k_hw_bitswap((ath_channel - 24) / 2, 8) & 0xff)
-			<< 2) | (clock << 1) | (1 << 10) | 1;
-	}
-
-	ath5k_hw_reg_write(hal, (data1 & 0xff) | ((data0 & 0xff) << 8),
-			AR5K_RF_BUFFER);
-	ath5k_hw_reg_write(hal, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
-			AR5K_RF_BUFFER_CONTROL_3);
-
-	return 0;
-}
-
-/*
- * Set channel on 5112
- */
-static int ath5k_hw_rf5112_channel(struct ath_hw *hal,
-		struct ieee80211_channel *channel)
-{
-	u32 data, data0, data1, data2;
-	u16 c;
-
-	data = data0 = data1 = data2 = 0;
-	c = channel->freq;
-
-	/*
-	 * Set the channel on the RF5112 or newer
-	 */
-	if (c < 4800) {
-		if (!((c - 2224) % 5)) {
-			data0 = ((2 * (c - 704)) - 3040) / 10;
-			data1 = 1;
-		} else if (!((c - 2192) % 5)) {
-			data0 = ((2 * (c - 672)) - 3040) / 10;
-			data1 = 0;
-		} else
-			return -EINVAL;
-
-		data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
-	} else {
-		if (!(c % 20) && c >= 5120) {
-			data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
-			data2 = ath5k_hw_bitswap(3, 2);
-		} else if (!(c % 10)) {
-			data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
-			data2 = ath5k_hw_bitswap(2, 2);
-		} else if (!(c % 5)) {
-			data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
-			data2 = ath5k_hw_bitswap(1, 2);
-		} else
-			return -EINVAL;
-	}
-
-	data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
-
-	ath5k_hw_reg_write(hal, data & 0xff, AR5K_RF_BUFFER);
-	ath5k_hw_reg_write(hal, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
-
-	return 0;
-}
-
-/*
- * Set a channel on the radio chip
- */
-static int ath5k_hw_channel(struct ath_hw *hal,
-		struct ieee80211_channel *channel)
-{
-	int ret;
-
-	/*
-	 * Check bounds supported by the PHY
-	 * (don't care about regulation restrictions at this point)
-	 */
-	if ((channel->freq < hal->ah_capabilities.cap_range.range_2ghz_min ||
-	    channel->freq > hal->ah_capabilities.cap_range.range_2ghz_max) &&
-	    (channel->freq < hal->ah_capabilities.cap_range.range_5ghz_min ||
-	    channel->freq > hal->ah_capabilities.cap_range.range_5ghz_max)) {
-		AR5K_PRINTF("channel out of supported range (%u MHz)\n",
-			channel->freq);
-		return -EINVAL;
-	}
-
-	/*
-	 * Set the channel and wait
-	 */
-	switch (hal->ah_radio) {
-	case AR5K_RF5110:
-		ret = ath5k_hw_rf5110_channel(hal, channel);
-		break;
-	case AR5K_RF5111:
-		ret = ath5k_hw_rf5111_channel(hal, channel);
-		break;
-	default:
-		ret = ath5k_hw_rf5112_channel(hal, channel);
-		break;
-	}
-
-	if (ret)
-		return ret;
-
-	hal->ah_current_channel.freq = channel->freq;
-	hal->ah_current_channel.val = channel->val;
-	hal->ah_turbo = channel->val == CHANNEL_T ? true : false;
-
-	return 0;
-}
-
-/*
- * Perform a PHY calibration on RF5110
- * -Fix BPSK/QAM Constellation (I/Q correction)
- * -Calculate Noise Floor
- */
-static int ath5k_hw_rf5110_calibrate(struct ath_hw *hal,
-		struct ieee80211_channel *channel)
-{
-	u32 phy_sig, phy_agc, phy_sat, beacon, noise_floor;
-	unsigned int i;
-	int ret;
-
-	/*
-	 * Disable beacons and RX/TX queues, wait
-	 */
-	AR5K_REG_ENABLE_BITS(hal, AR5K_DIAG_SW_5210,
-		AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
-	beacon = ath5k_hw_reg_read(hal, AR5K_BEACON_5210);
-	ath5k_hw_reg_write(hal, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
-
-	udelay(2300);
-
-	/*
-	 * Set the channel (with AGC turned off)
-	 */
-	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
-	udelay(10);
-	ret = ath5k_hw_channel(hal, channel);
-
-	/*
-	 * Activate PHY and wait
-	 */
-	ath5k_hw_reg_write(hal, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
-	mdelay(1);
-
-	AR5K_REG_DISABLE_BITS(hal, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
-
-	if (ret)
-		return ret;
-
-	/*
-	 * Calibrate the radio chip
-	 */
-
-	/* Remember normal state */
-	phy_sig = ath5k_hw_reg_read(hal, AR5K_PHY_SIG);
-	phy_agc = ath5k_hw_reg_read(hal, AR5K_PHY_AGCCOARSE);
-	phy_sat = ath5k_hw_reg_read(hal, AR5K_PHY_ADCSAT);
-
-	/* Update radio registers */
-	ath5k_hw_reg_write(hal, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
-		AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
-
-	ath5k_hw_reg_write(hal, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
-			AR5K_PHY_AGCCOARSE_LO)) |
-		AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
-		AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
-
-	ath5k_hw_reg_write(hal, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
-			AR5K_PHY_ADCSAT_THR)) |
-		AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
-		AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
-
-	udelay(20);
-
-	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
-	udelay(10);
-	ath5k_hw_reg_write(hal, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
-	AR5K_REG_DISABLE_BITS(hal, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
-
-	mdelay(1);
-
-	/*
-	 * Enable calibration and wait until completion
-	 */
-	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
-
-	ret = ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
-			AR5K_PHY_AGCCTL_CAL, 0, false);
-
-	/* Reset to normal state */
-	ath5k_hw_reg_write(hal, phy_sig, AR5K_PHY_SIG);
-	ath5k_hw_reg_write(hal, phy_agc, AR5K_PHY_AGCCOARSE);
-	ath5k_hw_reg_write(hal, phy_sat, AR5K_PHY_ADCSAT);
-
-	if (ret) {
-		AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq);
-		return ret;
-	}
-
-	/*
-	 * Enable noise floor calibration and wait until completion
-	 */
-	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF);
-
-	ret = ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
-			AR5K_PHY_AGCCTL_NF, 0, false);
-	if (ret) {
-		AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n",
-				channel->freq);
-		return ret;
-	}
-
-	/* Wait until the noise floor is calibrated */
-	for (i = 20; i > 0; i--) {
-		mdelay(1);
-		noise_floor = ath5k_hw_reg_read(hal, AR5K_PHY_NF);
-
-		if (AR5K_PHY_NF_RVAL(noise_floor) & AR5K_PHY_NF_ACTIVE)
-			noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
-
-		if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
-			break;
-	}
-
-	if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
-		AR5K_PRINTF("noise floor calibration failed (%uMHz)\n",
-			channel->freq);
-		return -EIO;
-	}
-
-	/*
-	 * Re-enable RX/TX and beacons
-	 */
-	AR5K_REG_DISABLE_BITS(hal, AR5K_DIAG_SW_5210,
-		AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
-	ath5k_hw_reg_write(hal, beacon, AR5K_BEACON_5210);
-
-	return 0;
-}
-
-/*
- * Perform a PHY calibration on RF5111/5112
- */
-static int ath5k_hw_rf511x_calibrate(struct ath_hw *hal,
-		struct ieee80211_channel *channel)
-{
-	u32 i_pwr, q_pwr;
-	s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
-	AR5K_TRACE;
-
-	if (hal->ah_calibration == false ||
-			ath5k_hw_reg_read(hal, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
-		goto done;
-
-	hal->ah_calibration = false;
-
-	iq_corr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_CORR);
-	i_pwr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_PWR_I);
-	q_pwr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_PWR_Q);
-	i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
-	q_coffd = q_pwr >> 6;
-
-	if (i_coffd == 0 || q_coffd == 0)
-		goto done;
-
-	i_coff = ((-iq_corr) / i_coffd) & 0x3f;
-	q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f;
-
-	/* Commit new IQ value */
-	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
-		((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
-
-done:
-	/* Start noise floor calibration */
-	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF);
-
-	/* Request RF gain */
-	if (channel->val & CHANNEL_5GHZ) {
-		ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txpower.txp_max,
-			AR5K_PHY_PAPD_PROBE_TXPOWER) |
-			AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
-		hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED;
-	}
-
-	return 0;
-}
-
-/*
- * Perform a PHY calibration
- */
-int ath5k_hw_phy_calibrate(struct ath_hw *hal,
-		struct ieee80211_channel *channel)
-{
-	int ret;
-
-	if (hal->ah_radio == AR5K_RF5110)
-		ret = ath5k_hw_rf5110_calibrate(hal, channel);
-	else
-		ret = ath5k_hw_rf511x_calibrate(hal, channel);
-
-	return ret;
-}
-
-bool
-ath5k_hw_phy_disable(struct ath_hw *hal)
-{
-	AR5K_TRACE;
-	/*Just a try M.F.*/
-	ath5k_hw_reg_write(hal, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
-	return true;
-}
-
-void /*TODO:Boundary check*/
-ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant)
-{
-	AR5K_TRACE;
-	/*Just a try M.F.*/
-	if (hal->ah_version != AR5K_AR5210)
-		ath5k_hw_reg_write(hal, ant, AR5K_DEFAULT_ANTENNA);
-}
-
-unsigned int
-ath5k_hw_get_def_antenna(struct ath_hw *hal)
-{
-	AR5K_TRACE;
-	/*Just a try M.F.*/
-	if (hal->ah_version != AR5K_AR5210)
-		return ath5k_hw_reg_read(hal, AR5K_DEFAULT_ANTENNA);
-
-	return false; /*XXX: What do we return for 5210 ?*/
-}
-
-/*
- * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
- */
-static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
-		u32 first, u32 col, bool set)
-{
-	u32 mask, entry, last, data, shift, position;
-	s32 left;
-	int i;
-
-	data = 0;
-
-	if (rf == NULL)
-		/* should not happen */
-		return 0;
-
-	if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {
-		AR5K_PRINTF("invalid values at offset %u\n", offset);
-		return 0;
-	}
-
-	entry = ((first - 1) / 8) + offset;
-	position = (first - 1) % 8;
-
-	if (set == true)
-		data = ath5k_hw_bitswap(reg, bits);
-
-	for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
-		last = (position + left > 8) ? 8 : position + left;
-		mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
-
-		if (set == true) {
-			rf[entry] &= ~mask;
-			rf[entry] |= ((data << position) << (col * 8)) & mask;
-			data >>= (8 - position);
-		} else {
-			data = (((rf[entry] & mask) >> (col * 8)) >> position)
-				<< shift;
-			shift += last - position;
-		}
-
-		left -= 8 - position;
-	}
-
-	data = set == true ? 1 : ath5k_hw_bitswap(data, bits);
-
-	return data;
-}
-
-static u32 ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal)
-{
-	u32 mix, step;
-	u32 *rf;
-
-	if (hal->ah_rf_banks == NULL)
-		return 0;
-
-	rf = hal->ah_rf_banks;
-	hal->ah_gain.g_f_corr = 0;
-
-	if (ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, false) != 1)
-		return 0;
-
-	step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, false);
-	mix = hal->ah_gain.g_step->gos_param[0];
-
-	switch (mix) {
-	case 3:
-		hal->ah_gain.g_f_corr = step * 2;
-		break;
-	case 2:
-		hal->ah_gain.g_f_corr = (step - 5) * 2;
-		break;
-	case 1:
-		hal->ah_gain.g_f_corr = step;
-		break;
-	default:
-		hal->ah_gain.g_f_corr = 0;
-		break;
-	}
-
-	return hal->ah_gain.g_f_corr;
-}
-
-static bool ath5k_hw_rfregs_gain_readback(struct ath_hw *hal)
-{
-	u32 step, mix, level[4];
-	u32 *rf;
-
-	if (hal->ah_rf_banks == NULL)
-		return false;
-
-	rf = hal->ah_rf_banks;
-
-	if (hal->ah_radio == AR5K_RF5111) {
-		step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 6, 37, 0,
-				false);
-		level[0] = 0;
-		level[1] = (step == 0x3f) ? 0x32 : step + 4;
-		level[2] = (step != 0x3f) ? 0x40 : level[0];
-		level[3] = level[2] + 0x32;
-
-		hal->ah_gain.g_high = level[3] -
-			(step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
-		hal->ah_gain.g_low = level[0] +
-			(step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
-	} else {
-		mix = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0,
-				false);
-		level[0] = level[2] = 0;
-
-		if (mix == 1) {
-			level[1] = level[3] = 83;
-		} else {
-			level[1] = level[3] = 107;
-			hal->ah_gain.g_high = 55;
-		}
-	}
-
-	return (hal->ah_gain.g_current >= level[0] &&
-			hal->ah_gain.g_current <= level[1]) ||
-		(hal->ah_gain.g_current >= level[2] &&
-			hal->ah_gain.g_current <= level[3]);
-}
-
-static s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal)
-{
-	const struct ath5k_gain_opt *go;
-	int ret = 0;
-
-	go = hal->ah_radio == AR5K_RF5111 ? &rf5111_gain_opt : &rf5112_gain_opt;
-
-	hal->ah_gain.g_step = &go->go_step[hal->ah_gain.g_step_idx];
-
-	if (hal->ah_gain.g_current >= hal->ah_gain.g_high) {
-		if (hal->ah_gain.g_step_idx == 0)
-			return -1;
-		for (hal->ah_gain.g_target = hal->ah_gain.g_current;
-				hal->ah_gain.g_target >=  hal->ah_gain.g_high &&
-				hal->ah_gain.g_step_idx > 0;
-				hal->ah_gain.g_step =
-					&go->go_step[hal->ah_gain.g_step_idx])
-			hal->ah_gain.g_target -= 2 *
-			    (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain -
-			    hal->ah_gain.g_step->gos_gain);
-
-		ret = 1;
-		goto done;
-	}
-
-	if (hal->ah_gain.g_current <= hal->ah_gain.g_low) {
-		if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1))
-			return -2;
-		for (hal->ah_gain.g_target = hal->ah_gain.g_current;
-				hal->ah_gain.g_target <= hal->ah_gain.g_low &&
-				hal->ah_gain.g_step_idx < go->go_steps_count-1;
-				hal->ah_gain.g_step =
-					&go->go_step[hal->ah_gain.g_step_idx])
-			hal->ah_gain.g_target -= 2 *
-			    (go->go_step[++hal->ah_gain.g_step_idx].gos_gain -
-			    hal->ah_gain.g_step->gos_gain);
-
-		ret = 2;
-		goto done;
-	}
-
-done:
-#ifdef AR5K_DEBUG
-	AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n",
-		ret, hal->ah_gain.g_step_idx, hal->ah_gain.g_current,
-		hal->ah_gain.g_target);
-#endif
-
-	return ret;
-}
-
-/*
- * Initialize RF
- */
-static int ath5k_hw_rfregs(struct ath_hw *hal,
-		struct ieee80211_channel *channel, unsigned int mode)
-{
-	int (*func)(struct ath_hw *, struct ieee80211_channel *, unsigned int);
-	int ret;
-
-	switch (hal->ah_radio) {
-	case AR5K_RF5111:
-		hal->ah_rf_banks_size = sizeof(rf5111_rf);
-		func = ath5k_hw_rf5111_rfregs;
-		break;
-	case AR5K_RF5112:
-		if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
-			hal->ah_rf_banks_size = sizeof(rf5112a_rf);
-		else
-		hal->ah_rf_banks_size = sizeof(rf5112_rf);
-		func = ath5k_hw_rf5112_rfregs;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	if (hal->ah_rf_banks == NULL) {
-		/* XXX do extra checks? */
-		hal->ah_rf_banks = kmalloc(hal->ah_rf_banks_size, GFP_KERNEL);
-		if (hal->ah_rf_banks == NULL) {
-			AR5K_PRINT("out of memory\n");
-			return -ENOMEM;
-		}
-	}
-
-	ret = func(hal, channel, mode);
-	if (!ret)
-		hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
-
-	return ret;
-}
-
-/*
- * Read EEPROM Calibration data, modify RF Banks and Initialize RF5111
- */
-static int ath5k_hw_rf5111_rfregs(struct ath_hw *hal,
-		struct ieee80211_channel *channel, unsigned int mode)
-{
-	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
-	u32 *rf;
-	const unsigned int rf_size = ARRAY_SIZE(rf5111_rf);
-	unsigned int i;
-	int obdb = -1, bank = -1;
-	u32 ee_mode;
-
-	AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
-
-	rf = hal->ah_rf_banks;
-
-	/* Copy values to modify them */
-	for (i = 0; i < rf_size; i++) {
-		if (rf5111_rf[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
-			AR5K_PRINT("invalid bank\n");
-			return -EINVAL;
-		}
-
-		if (bank != rf5111_rf[i].rf_bank) {
-			bank = rf5111_rf[i].rf_bank;
-			hal->ah_offset[bank] = i;
-		}
-
-		rf[i] = rf5111_rf[i].rf_value[mode];
-	}
-
-	/* Modify bank 0 */
-	if (channel->val & CHANNEL_2GHZ) {
-		if (channel->val & CHANNEL_B)
-			ee_mode = AR5K_EEPROM_MODE_11B;
-		else
-			ee_mode = AR5K_EEPROM_MODE_11G;
-		obdb = 0;
-
-		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0],
-				ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
-			return -EINVAL;
-
-		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0],
-				ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
-			return -EINVAL;
-
-		obdb = 1;
-	/* Modify bank 6 */
-	} else {
-		/* For 11a, Turbo and XR */
-		ee_mode = AR5K_EEPROM_MODE_11A;
-		obdb =	 channel->freq >= 5725 ? 3 :
-			(channel->freq >= 5500 ? 2 :
-			(channel->freq >= 5260 ? 1 :
-			 (channel->freq > 4000 ? 0 : -1)));
-
-		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-				ee->ee_pwd_84, 1, 51, 3, true))
-			return -EINVAL;
-
-		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-				ee->ee_pwd_90, 1, 45, 3, true))
-			return -EINVAL;
-	}
-
-	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-			!ee->ee_xpd[ee_mode], 1, 95, 0, true))
-		return -EINVAL;
-
-	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-			ee->ee_x_gain[ee_mode], 4, 96, 0, true))
-		return -EINVAL;
-
-	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], obdb >= 0 ?
-			ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
-		return -EINVAL;
-
-	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], obdb >= 0 ?
-			ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
-		return -EINVAL;
-
-	/* Modify bank 7 */
-	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
-			ee->ee_i_gain[ee_mode], 6, 29, 0, true))
-		return -EINVAL;
-
-	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
-			ee->ee_xpd[ee_mode], 1, 4, 0, true))
-		return -EINVAL;
-
-	/* Write RF values */
-	for (i = 0; i < rf_size; i++) {
-		AR5K_REG_WAIT(i);
-		ath5k_hw_reg_write(hal, rf[i], rf5111_rf[i].rf_register);
-	}
-
-	return 0;
-}
-
-/*
- * Read EEPROM Calibration data, modify RF Banks and Initialize RF5112
- */
-static int ath5k_hw_rf5112_rfregs(struct ath_hw *hal,
-		struct ieee80211_channel *channel, unsigned int mode)
-{
-	const struct ath5k_ini_rf *rf_ini;
-	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
-	u32 *rf;
-	unsigned int rf_size, i;
-	int obdb = -1, bank = -1;
-	u32 ee_mode;
-
-	AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
-
-	rf = hal->ah_rf_banks;
-
-	if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
-		rf_ini = rf5112a_rf;
-		rf_size = ARRAY_SIZE(rf5112a_rf);
-	} else {
-		rf_ini = rf5112_rf;
-		rf_size = ARRAY_SIZE(rf5112_rf);
-	}
-
-	/* Copy values to modify them */
-	for (i = 0; i < rf_size; i++) {
-		if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
-			AR5K_PRINT("invalid bank\n");
-			return -EINVAL;
-		}
-
-		if (bank != rf_ini[i].rf_bank) {
-			bank = rf_ini[i].rf_bank;
-			hal->ah_offset[bank] = i;
-		}
-
-		rf[i] = rf_ini[i].rf_value[mode];
-	}
-
-	/* Modify bank 6 */
-	if (channel->val & CHANNEL_2GHZ) {
-		if (channel->val & CHANNEL_B)
-			ee_mode = AR5K_EEPROM_MODE_11B;
-		else
-			ee_mode = AR5K_EEPROM_MODE_11G;
-		obdb = 0;
-
-		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-				ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
-			return -EINVAL;
-
-		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-				ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
-			return -EINVAL;
-	} else {
-		/* For 11a, Turbo and XR */
-		ee_mode = AR5K_EEPROM_MODE_11A;
-		obdb = channel->freq >= 5725 ? 3 :
-		    (channel->freq >= 5500 ? 2 :
-			(channel->freq >= 5260 ? 1 :
-			    (channel->freq > 4000 ? 0 : -1)));
-
-		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-				ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
-			return -EINVAL;
-
-		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-				ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
-			return -EINVAL;
-	}
-
-#ifdef notyet
-	ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-	    ee->ee_x_gain[ee_mode], 2, 270, 0, true);
-	ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-	    ee->ee_x_gain[ee_mode], 2, 257, 0, true);
-#endif
-
-	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-			ee->ee_xpd[ee_mode], 1, 302, 0, true))
-		return -EINVAL;
-
-	/* Modify bank 7 */
-	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
-			ee->ee_i_gain[ee_mode], 6, 14, 0, true))
-		return -EINVAL;
-
-	/* Write RF values */
-	for (i = 0; i < rf_size; i++)
-		ath5k_hw_reg_write(hal, rf[i], rf_ini[i].rf_register);
-
-	return 0;
-}
-
-static int ath5k_hw_rfgain(struct ath_hw *hal, unsigned int freq)
-{
-	const struct ath5k_ini_rfgain *ath5k_rfg;
-	unsigned int i, size;
-
-	switch (hal->ah_radio) {
-	case AR5K_RF5111:
-		ath5k_rfg = rf5111_ini_rfgain;
-		size = ARRAY_SIZE(rf5111_ini_rfgain);
-		break;
-	case AR5K_RF5112:
-		ath5k_rfg = rf5112_ini_rfgain;
-		size = ARRAY_SIZE(rf5112_ini_rfgain);
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	switch (freq) {
-	case AR5K_INI_RFGAIN_2GHZ:
-	case AR5K_INI_RFGAIN_5GHZ:
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	for (i = 0; i < size; i++) {
-		AR5K_REG_WAIT(i);
-		ath5k_hw_reg_write(hal, ath5k_rfg[i].rfg_value[freq],
-			(u32)ath5k_rfg[i].rfg_register);
-	}
-
-	return 0;
-}
-
-enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal)
-{
-	u32 data, type;
-
-	AR5K_TRACE;
-
-	if (hal->ah_rf_banks == NULL || !hal->ah_gain.g_active ||
-			hal->ah_version <= AR5K_AR5211)
-		return AR5K_RFGAIN_INACTIVE;
-
-	if (hal->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED)
-		goto done;
-
-	data = ath5k_hw_reg_read(hal, AR5K_PHY_PAPD_PROBE);
-
-	if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
-		hal->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
-		type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
-
-		if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK)
-			hal->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR;
-
-		if (hal->ah_radio == AR5K_RF5112) {
-			ath5k_hw_rfregs_gainf_corr(hal);
-			hal->ah_gain.g_current =
-				hal->ah_gain.g_current>=hal->ah_gain.g_f_corr ?
-				(hal->ah_gain.g_current-hal->ah_gain.g_f_corr) :
-				0;
-		}
-
-		if (ath5k_hw_rfregs_gain_readback(hal) &&
-				AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) &&
-				ath5k_hw_rfregs_gain_adjust(hal))
-			hal->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE;
-	}
-
-done:
-	return hal->ah_rf_gain;
-}
-
-/*
- * TX power setup
- */
-
-/*
- * Initialize the tx power table (not fully implemented)
- */
-static void ath5k_txpower_table(struct ath_hw *hal,
-		struct ieee80211_channel *channel, s16 max_power)
-{
-	unsigned int i, min, max, n;
-	u16 txpower, *rates;
-
-	rates = hal->ah_txpower.txp_rates;
-
-	txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2;
-	if (max_power > txpower)
-		txpower = max_power > AR5K_TUNE_MAX_TXPOWER ?
-		    AR5K_TUNE_MAX_TXPOWER : max_power;
-
-	for (i = 0; i < AR5K_MAX_RATES; i++)
-		rates[i] = txpower;
-
-	/* XXX setup target powers by rate */
-
-	hal->ah_txpower.txp_min = rates[7];
-	hal->ah_txpower.txp_max = rates[0];
-	hal->ah_txpower.txp_ofdm = rates[0];
-
-	/* Calculate the power table */
-	n = ARRAY_SIZE(hal->ah_txpower.txp_pcdac);
-	min = AR5K_EEPROM_PCDAC_START;
-	max = AR5K_EEPROM_PCDAC_STOP;
-	for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP)
-		hal->ah_txpower.txp_pcdac[i] =
-#ifdef notyet
-		min + ((i * (max - min)) / n);
-#else
-		min;
-#endif
-}
-
-/*
- * Set transmition power
- */
-static int /*O.K. - txpower_table is unimplemented so this doesn't work*/
-ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel,
-		unsigned int txpower)
-{
-	bool tpc = hal->ah_txpower.txp_tpc;
-	unsigned int i;
-
-	AR5K_TRACE;
-	if (txpower > AR5K_TUNE_MAX_TXPOWER) {
-		AR5K_PRINTF("invalid tx power: %u\n", txpower);
-		return -EINVAL;
-	}
-
-	/* Reset TX power values */
-	memset(&hal->ah_txpower, 0, sizeof(hal->ah_txpower));
-	hal->ah_txpower.txp_tpc = tpc;
-
-	/* Initialize TX power table */
-	ath5k_txpower_table(hal, channel, txpower);
-
-	/*
-	 * Write TX power values
-	 */
-	for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
-		ath5k_hw_reg_write(hal,
-			((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) |
-			(((hal->ah_txpower.txp_pcdac[(i << 1)    ] << 8) | 0xff) & 0xffff),
-			AR5K_PHY_PCDAC_TXPOWER(i));
-	}
-
-	ath5k_hw_reg_write(hal, AR5K_TXPOWER_OFDM(3, 24) |
-		AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
-		AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
-
-	ath5k_hw_reg_write(hal, AR5K_TXPOWER_OFDM(7, 24) |
-		AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
-		AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
-
-	ath5k_hw_reg_write(hal, AR5K_TXPOWER_CCK(10, 24) |
-		AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
-		AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
-
-	ath5k_hw_reg_write(hal, AR5K_TXPOWER_CCK(14, 24) |
-		AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
-		AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
-
-	if (hal->ah_txpower.txp_tpc == true)
-		ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
-			AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
-	else
-		ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX |
-			AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
-
-	return 0;
-}
-
-int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power)
-{
-	/*Just a try M.F.*/
-	struct ieee80211_channel *channel = &hal->ah_current_channel;
-
-	AR5K_TRACE;
-#ifdef AR5K_DEBUG
-	AR5K_PRINTF("changing txpower to %d\n", power);
-#endif
-	return ath5k_hw_txpower(hal, channel, power);
-}
-
-
 
 
 /****************\

commit b80066d2e1db5d153a36361821cf5cf505d18c54
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Sat Aug 25 08:50:56 2007 +0200

    add missing break; in rfgain

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 6ee7f09..47fc6f2 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -5321,6 +5321,7 @@ static int ath5k_hw_rfgain(struct ath_hw *hal, unsigned int freq)
 	case AR5K_RF5112:
 		ath5k_rfg = rf5112_ini_rfgain;
 		size = ARRAY_SIZE(rf5112_ini_rfgain);
+		break;
 	default:
 		return -EINVAL;
 	}

commit 7435ea363364c65f32d26df1810cd234401829f6
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Sat Aug 25 08:41:43 2007 +0200

    remove some ieee80211 re-defines

diff --git a/ath5k_hw.c b/ath5k_hw.c
index bc60794..6ee7f09 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -142,15 +142,16 @@ ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates,
 	 * Calculate the transmission time by operation (PHY) mode
 	 */
 	switch (rate->modulation) {
-	case MODULATION_CCK:
+	case IEEE80211_RATE_CCK:
 		/*
 		 * CCK / DS mode (802.11b)
 		 */
 		value = AR5K_CCK_TX_TIME(rate->rate_kbps, frame_length,
-		    (short_preamble && (rate->modulation == MODULATION_CCK_SP)));
+			short_preamble &&
+			rate->modulation == IEEE80211_RATE_CCK_2);
 		break;
 
-	case MODULATION_OFDM:
+	case IEEE80211_RATE_OFDM:
 		/*
 		 * Orthogonal Frequency Division Multiplexing
 		 */
@@ -159,7 +160,7 @@ ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates,
 		value = AR5K_OFDM_TX_TIME(rate->rate_kbps, frame_length);
 		break;
 
-	case MODULATION_TURBO:
+	case IEEE80211_RATE_TURBO:
 		/*
 		 * Orthogonal Frequency Division Multiplexing
 		 * Atheros "Turbo Mode" (doubled rates)

commit 5b723f6fa54d89da777d81793c4893f7a25afbb2
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Sat Aug 25 08:02:46 2007 +0200

    comment some registers

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 326af52..bc60794 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -4673,6 +4673,8 @@ static int ath5k_hw_channel(struct ath_hw *hal,
 
 /*
  * Perform a PHY calibration on RF5110
+ * -Fix BPSK/QAM Constellation (I/Q correction)
+ * -Calculate Noise Floor
  */
 static int ath5k_hw_rf5110_calibrate(struct ath_hw *hal,
 		struct ieee80211_channel *channel)

commit 64dbd8a621605c0c9bf3d73fcc8b293d0e15e8b7
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Fri Aug 24 23:32:08 2007 +0200

    backport r2595

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 5f0aa32..326af52 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -70,40 +70,43 @@ static int ath5k_hw_rf5111_rfregs(struct ath_hw *, struct ieee80211_channel *,
 		unsigned int);
 static int ath5k_hw_rf5112_rfregs(struct ath_hw *, struct ieee80211_channel *,
 		unsigned int);
-static void ath5k_hw_ar5211_rfregs(struct ath_hw *, struct ieee80211_channel *,
-		unsigned int, unsigned int);
+static int ath5k_hw_rfgain(struct ath_hw *, unsigned int);
 
 /*
  * Initial register dumps
  */
+
+/*
+ * MAC/PHY Settings
+ */
+/* Common for all modes */
 static const struct ath5k_ini ar5210_ini[] = AR5K_AR5210_INI;
 static const struct ath5k_ini ar5211_ini[] = AR5K_AR5211_INI;
 static const struct ath5k_ini ar5212_ini[] = AR5K_AR5212_INI;
-static const struct ath5k_ar5211_ini_mode ar5211_mode[] = AR5K_AR5211_INI_MODE;
-static const struct ath5k_ar5212_ini_mode ar5212_mode[] = AR5K_AR5212_INI_MODE;
 
-/* RF Initial BB gain settings */
-static const struct ath5k_ini rf5111_bbgain_ini[] = AR5K_RF5111_BBGAIN_INI;
-static const struct ath5k_ini rf5112_bbgain_ini[] = AR5K_RF5112_BBGAIN_INI;
-
-/* This is going out soon */
-static const struct ath5k_ar5211_ini_rf ar5211_rf[] = AR5K_AR5211_INI_RF;
+/* Mode-specific settings */
+static const struct ath5k_ini_mode ar5211_ini_mode[] = AR5K_AR5211_INI_MODE;
+static const struct ath5k_ini_mode ar5212_ini_mode[] = AR5K_AR5212_INI_MODE;
+static const struct ath5k_ini_mode ar5212_rf5111_ini_mode[] = AR5K_AR5212_RF5111_INI_MODE;
+static const struct ath5k_ini_mode ar5212_rf5112_ini_mode[] = AR5K_AR5212_RF5112_INI_MODE;
 
-/*
- * Initial gain optimization values
- */
-static const struct ath5k_gain_opt rf5111_gain_opt = AR5K_RF5111_GAIN_OPT;
-static const struct ath5k_gain_opt rf5112_gain_opt = AR5K_RF5112_GAIN_OPT;
+/* RF Initial BB gain settings */
+static const struct ath5k_ini rf5111_ini_bbgain[] = AR5K_RF5111_INI_BBGAIN;
+static const struct ath5k_ini rf5112_ini_bbgain[] = AR5K_RF5112_INI_BBGAIN;
 
 /*
- * Initial register settings for the radio chipsets
+ * RF Settings
  */
 /* RF Banks */
 static const struct ath5k_ini_rf rf5111_rf[] = AR5K_RF5111_INI_RF;
 static const struct ath5k_ini_rf rf5112_rf[] = AR5K_RF5112_INI_RF;
 static const struct ath5k_ini_rf rf5112a_rf[] = AR5K_RF5112A_INI_RF;
-/* Common (5111/5112) rf gain table */
-static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN;
+/* Initial mode-specific RF gain table for 5111/5112 */
+static const struct ath5k_ini_rfgain rf5111_ini_rfgain[] = AR5K_RF5111_INI_RFGAIN;
+static const struct ath5k_ini_rfgain rf5112_ini_rfgain[] = AR5K_RF5112_INI_RFGAIN;
+/* Initial gain optimization tables */
+static const struct ath5k_gain_opt rf5111_gain_opt = AR5K_RF5111_GAIN_OPT;
+static const struct ath5k_gain_opt rf5112_gain_opt = AR5K_RF5112_GAIN_OPT;
 
 /*
  * Enable to overwrite the country code (use "00" for debug)
@@ -257,6 +260,8 @@ static void ath5k_hw_ini_registers(struct ath_hw *hal, unsigned int size,
 
 	/* Write initial registers */
 	for (i = 0; i < size; i++) {
+		/* On channel change there is
+		 * no need to mess with PCU */
 		if (change_channel &&
 				ini_regs[i].ini_register >= AR5K_PCU_MIN &&
 				ini_regs[i].ini_register <= AR5K_PCU_MAX)
@@ -276,6 +281,20 @@ static void ath5k_hw_ini_registers(struct ath_hw *hal, unsigned int size,
 	}
 }
 
+static void ath5k_hw_ini_mode_registers(struct ath_hw *hal,
+		unsigned int size, const struct ath5k_ini_mode *ini_mode,
+		u8 mode)
+{
+	unsigned int i;
+
+	for (i = 0; i < size; i++) {
+		AR5K_REG_WAIT(i);
+		ath5k_hw_reg_write(hal, ini_mode[i].mode_value[mode],
+			(u32)ini_mode[i].mode_register);
+	}
+
+}
+
 /***************************************\
 	Attach/Detach Functions
 \***************************************/
@@ -291,8 +310,6 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc,
 	int ret;
 	u32 srev;
 
-	/*TODO:Use eeprom_magic to verify chipset*/
-
 	/*If we passed the test malloc a hal struct*/
 	hal = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
 	if (hal == NULL) {
@@ -500,24 +517,34 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial)
 		if (flags & CHANNEL_2GHZ) {
 			mode |= AR5K_PHY_MODE_FREQ_2GHZ;
 			clock |= AR5K_PHY_PLL_44MHZ;
+
+			if (flags & CHANNEL_CCK) {
+				mode |= AR5K_PHY_MODE_MOD_CCK;
+			} else if (flags & CHANNEL_OFDM) {
+				/* XXX Dynamic OFDM/CCK is not supported by the
+				 * AR5211 so we set MOD_OFDM for plain g (no
+				 * CCK headers) operation. We need to test
+				 * this, 5211 might support ofdm-only g after
+				 * all, there are also initial register values
+				 * in the code for g mode (see ath5k_hw.h). */
+				if (hal->ah_version == AR5K_AR5211)
+					mode |= AR5K_PHY_MODE_MOD_OFDM;
+				else
+					mode |= AR5K_PHY_MODE_MOD_DYN;
+			} else {
+				AR5K_PRINT("invalid radio modulation mode\n");
+				return -EINVAL;
+			}
 		} else if (flags & CHANNEL_5GHZ) {
 			mode |= AR5K_PHY_MODE_FREQ_5GHZ;
 			clock |= AR5K_PHY_PLL_40MHZ;
-		} else {
-			AR5K_PRINT("invalid radio frequency mode\n");
-			return -EINVAL;
-		}
 
-		if (flags & CHANNEL_CCK) {
-			mode |= AR5K_PHY_MODE_MOD_CCK;
-		} else if (flags & CHANNEL_G) {
-			/* Dynamic OFDM/CCK is not supported by the AR5211 */
-			if (hal->ah_version == AR5K_AR5211)
-				mode |= AR5K_PHY_MODE_MOD_CCK;
-			else
-				mode |= AR5K_PHY_MODE_MOD_DYN;
-		} else if (flags & CHANNEL_OFDM) {
-			mode |= AR5K_PHY_MODE_MOD_OFDM;
+			if (flags & CHANNEL_OFDM)
+				mode |= AR5K_PHY_MODE_MOD_OFDM;
+			else {
+				AR5K_PRINT("invalid radio modulation mode\n");
+				return -EINVAL;
+			}
 		} else {
 			AR5K_PRINT("invalid radio frequency mode\n");
 			return -EINVAL;
@@ -642,7 +669,6 @@ static u16 ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan)
 
 /*
  * Get the rate table for a specific operation mode
- * TODO:Limit this per chipset
  */
 const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal,
 		unsigned int mode)
@@ -697,7 +723,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
 	u32 data, noise_floor, s_seq, s_ant, s_led[3];
 	u8 mac[ETH_ALEN];
-	unsigned int i, phy, mode, freq, off, ee_mode, ant[2];
+	unsigned int i, mode, freq, ee_mode, ant[2];
 	int ret;
 
 	AR5K_TRACE;
@@ -707,7 +733,6 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 	ee_mode = 0;
 	freq = 0;
 	mode = 0;
-	phy = 0;
 
 	/*
 	 * Save some registers before a reset
@@ -747,11 +772,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 	 * 5210 only comes with RF5110
 	 */
 	if (hal->ah_version != AR5K_AR5210) {
-		if (hal->ah_radio == AR5K_RF5111)
-			phy = AR5K_INI_PHY_5111;
-		else if (hal->ah_radio == AR5K_RF5112)
-			phy = AR5K_INI_PHY_5112;
-		else {
+		if (hal->ah_radio != AR5K_RF5111 &&
+				hal->ah_radio != AR5K_RF5112) {
 			AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio);
 			return -EINVAL;
 		}
@@ -767,6 +789,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 			freq = AR5K_INI_RFGAIN_2GHZ;
 			ee_mode = AR5K_EEPROM_MODE_11B;
 			break;
+		/* Is this ok on 5211 too ? */
 		case CHANNEL_G:
 			mode = AR5K_INI_VAL_11G;
 			freq = AR5K_INI_RFGAIN_2GHZ;
@@ -800,51 +823,32 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 		/* PHY access enable */
 		ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
 
-		/*
-		 * Write initial RF registers on 5211
-		 * do we need that ? Is ath5k_hw_rfregs going to work for
-		 * 5211 (5111) ?
-		 */
-		if (hal->ah_version == AR5K_AR5211)
-			ath5k_hw_ar5211_rfregs(hal, channel, freq, ee_mode);
 	}
 
 	/*
-	 * Write initial mode settings
-	 * TODO:Do this in a common way
+	 * Write initial mode-specific settings
 	 */
 	/*For 5212*/
 	if (hal->ah_version == AR5K_AR5212) {
-		for (i = 0; i < ARRAY_SIZE(ar5212_mode); i++) {
-			if (ar5212_mode[i].mode_flags == AR5K_INI_FLAG_511X)
-				off = AR5K_INI_PHY_511X;
-			else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5111
-					&& hal->ah_radio == AR5K_RF5111)
-				off = AR5K_INI_PHY_5111;
-			else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5112
-					&& hal->ah_radio == AR5K_RF5112)
-				off = AR5K_INI_PHY_5112;
-			else
-				continue;
-
-			AR5K_REG_WAIT(i);
-			ath5k_hw_reg_write(hal,
-					ar5212_mode[i].mode_value[off][mode],
-					(u32)ar5212_mode[i].mode_register);
-		}
+		ath5k_hw_ini_mode_registers(hal, ARRAY_SIZE(ar5212_ini_mode),
+				ar5212_ini_mode, mode);
+		if (hal->ah_radio == AR5K_RF5111)
+			ath5k_hw_ini_mode_registers(hal,
+					ARRAY_SIZE(ar5212_rf5111_ini_mode),
+					ar5212_rf5111_ini_mode, mode);
+		else if (hal->ah_radio == AR5K_RF5112)
+			ath5k_hw_ini_mode_registers(hal,
+					ARRAY_SIZE(ar5212_rf5112_ini_mode),
+					ar5212_rf5112_ini_mode, mode);
 	}
 	/*For 5211*/
-	if (hal->ah_version == AR5K_AR5211) {
-		for (i = 0; i < ARRAY_SIZE(ar5211_mode); i++) {
-			AR5K_REG_WAIT(i);
-			ath5k_hw_reg_write(hal,
-				ar5211_mode[i].mode_value[mode],
-				(u32)ar5211_mode[i].mode_register);
-		}
-	}
+	if (hal->ah_version == AR5K_AR5211)
+		ath5k_hw_ini_mode_registers(hal, ARRAY_SIZE(ar5211_ini_mode),
+				ar5211_ini_mode, mode);
+	/* For 5210 mode settings check out ath5k_hw_reset_tx_queue */
 
 	/*
-	 * Initial register dump common for all modes
+	 * Write initial settings common for all modes
 	 */
 	/*For 5212*/
 	if (hal->ah_version == AR5K_AR5212) {
@@ -854,23 +858,23 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 			ath5k_hw_reg_write(hal, AR5K_PHY_PAPD_PROBE_INI_5112,
 					AR5K_PHY_PAPD_PROBE);
 			ath5k_hw_ini_registers(hal,
-					ARRAY_SIZE(rf5112_bbgain_ini),
-					rf5112_bbgain_ini, change_channel);
+					ARRAY_SIZE(rf5112_ini_bbgain),
+					rf5112_ini_bbgain, change_channel);
 		} else if (hal->ah_radio == AR5K_RF5111) {
 			ath5k_hw_reg_write(hal, AR5K_PHY_GAIN_2GHZ_INI_5111,
 					AR5K_PHY_GAIN_2GHZ);
 			ath5k_hw_reg_write(hal, AR5K_PHY_PAPD_PROBE_INI_5111,
 					AR5K_PHY_PAPD_PROBE);
 			ath5k_hw_ini_registers(hal,
-					ARRAY_SIZE(rf5111_bbgain_ini),
-					rf5111_bbgain_ini, change_channel);
+					ARRAY_SIZE(rf5111_ini_bbgain),
+					rf5111_ini_bbgain, change_channel);
 		}
 	} else if (hal->ah_version == AR5K_AR5211) {
 		ath5k_hw_ini_registers(hal, ARRAY_SIZE(ar5211_ini),
 				ar5211_ini, change_channel);
 		/* AR5211 only comes with 5111 */
-		ath5k_hw_ini_registers(hal, ARRAY_SIZE(rf5111_bbgain_ini),
-				rf5111_bbgain_ini, change_channel);
+		ath5k_hw_ini_registers(hal, ARRAY_SIZE(rf5111_ini_bbgain),
+				rf5111_ini_bbgain, change_channel);
 	} else if (hal->ah_version == AR5K_AR5210) {
 		ath5k_hw_ini_registers(hal, ARRAY_SIZE(ar5210_ini),
 				ar5210_ini, change_channel);
@@ -884,8 +888,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 		 * Write initial RF gain settings
 		 * This should work for both 5111/5112
 		 */
-		if (ath5k_hw_rfgain(hal, phy, freq) == false)
-			return -EIO;
+		ret = ath5k_hw_rfgain(hal, freq);
+		if (ret)
+			return ret;
 
 		mdelay(1);
 
@@ -1945,6 +1950,9 @@ static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data)
 	return -EIO;
 }
 
+/*
+ * Translate binary channel representation in EEPROM to frequency
+ */
 static u16 ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode)
 {
 	u16 val;
@@ -3371,9 +3379,6 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 {
 	u32 cw_min, cw_max, retry_lg, retry_sh;
 	struct ath5k_txq_info *tq = &hal->ah_txq[queue];
-	int i;
-	struct ath5k_ar5210_ini_mode ar5210_mode[] =
-			AR5K_AR5210_INI_MODE(hal, hal->ah_aifs + tq->tqi_aifs);
 
 	AR5K_TRACE;
 	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
@@ -3388,14 +3393,46 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 		if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
 			return -EINVAL;
 
-		/*
-		 * Write initial mode register settings
-		 */
-		for (i = 0; i < ARRAY_SIZE(ar5210_mode); i++)
-			ath5k_hw_reg_write(hal, hal->ah_turbo == true ?
-				ar5210_mode[i].mode_turbo :
-				ar5210_mode[i].mode_base,
-				(u32)ar5210_mode[i].mode_register);
+		/* Set Slot time */
+		ath5k_hw_reg_write(hal, hal->ah_turbo == true ?
+			AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
+			AR5K_SLOT_TIME);
+		/* Set ACK_CTS timeout */
+		ath5k_hw_reg_write(hal, hal->ah_turbo == true ?
+			AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
+			AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
+		/* Set Transmit Latency */
+		ath5k_hw_reg_write(hal, hal->ah_turbo == true ?
+			AR5K_INIT_TRANSMIT_LATENCY_TURBO :
+			AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);
+		/* Set IFS0 */
+		if (hal->ah_turbo == true)
+			 ath5k_hw_reg_write(hal, ((AR5K_INIT_SIFS_TURBO +
+				(hal->ah_aifs + tq->tqi_aifs) *
+				AR5K_INIT_SLOT_TIME_TURBO) <<
+				AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
+				AR5K_IFS0);
+		else
+			ath5k_hw_reg_write(hal, ((AR5K_INIT_SIFS +
+				(hal->ah_aifs + tq->tqi_aifs) *
+				AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) |
+				AR5K_INIT_SIFS, AR5K_IFS0);
+
+		/* Set IFS1 */
+		ath5k_hw_reg_write(hal, hal->ah_turbo == true ?
+			AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
+			AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
+		/* Set PHY register 0x9844 (??) */
+		ath5k_hw_reg_write(hal, hal->ah_turbo == true ?
+			(ath5k_hw_reg_read(hal, AR5K_PHY(17)) & ~0x7F) | 0x38 :
+			(ath5k_hw_reg_read(hal, AR5K_PHY(17)) & ~0x7F) | 0x1C,
+			AR5K_PHY(17));
+		/* Set Frame Control Register */
+		ath5k_hw_reg_write(hal, hal->ah_turbo == true ?
+			(AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
+			AR5K_PHY_TURBO_SHORT | 0x2020) :
+			(AR5K_PHY_FRAME_CTL_INI | 0x1020),
+			AR5K_PHY_FRAME_CTL_5210);
 	}
 
 	/*
@@ -4855,6 +4892,9 @@ ath5k_hw_get_def_antenna(struct ath_hw *hal)
 	return false; /*XXX: What do we return for 5210 ?*/
 }
 
+/*
+ * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
+ */
 static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
 		u32 first, u32 col, bool set)
 {
@@ -5070,7 +5110,7 @@ static int ath5k_hw_rfregs(struct ath_hw *hal,
 }
 
 /*
- * Initialize RF5111
+ * Read EEPROM Calibration data, modify RF Banks and Initialize RF5111
  */
 static int ath5k_hw_rf5111_rfregs(struct ath_hw *hal,
 		struct ieee80211_channel *channel, unsigned int mode)
@@ -5171,7 +5211,7 @@ static int ath5k_hw_rf5111_rfregs(struct ath_hw *hal,
 }
 
 /*
- * Initialize RF5112
+ * Read EEPROM Calibration data, modify RF Banks and Initialize RF5112
  */
 static int ath5k_hw_rf5112_rfregs(struct ath_hw *hal,
 		struct ieee80211_channel *channel, unsigned int mode)
@@ -5265,81 +5305,21 @@ static int ath5k_hw_rf5112_rfregs(struct ath_hw *hal,
 	return 0;
 }
 
-/*
- * Initialize 5211 RF
- * TODO: is this needed ? i mean 5211 has a 5111 RF
- * doesn't ar5k_rfregs work ?
- */
-static void ath5k_hw_ar5211_rfregs(struct ath_hw *hal,
-		struct ieee80211_channel *channel, unsigned int freq,
-		unsigned int ee_mode)
+static int ath5k_hw_rfgain(struct ath_hw *hal, unsigned int freq)
 {
-	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
-	struct ath5k_ar5211_ini_rf rf[ARRAY_SIZE(ar5211_rf)];
-	u32 ob, db, obdb, xpds, xpdp, x_gain;
-	unsigned int i;
-
-	memcpy(rf, ar5211_rf, sizeof(rf));
-	obdb = 0;
-
-	if (freq == AR5K_INI_RFGAIN_2GHZ &&
-		hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_1) {
-			ob = ath5k_hw_bitswap(ee->ee_ob[ee_mode][0], 3);
-			db = ath5k_hw_bitswap(ee->ee_db[ee_mode][0], 3);
-		rf[25].rf_value[freq] =
-			((ob << 6) & 0xc0) | (rf[25].rf_value[freq] & ~0xc0);
-		rf[26].rf_value[freq] =
-			(((ob >> 2) & 0x1) | ((db << 1) & 0xe)) |
-			(rf[26].rf_value[freq] & ~0xf);
-	}
+	const struct ath5k_ini_rfgain *ath5k_rfg;
+	unsigned int i, size;
 
-	if (freq == AR5K_INI_RFGAIN_5GHZ) {
-		/* For 11a and Turbo */
-		obdb =	 channel->freq >= 5725 ? 3 :
-			(channel->freq >= 5500 ? 2 :
-			(channel->freq >= 5260 ? 1 :
-			(channel->freq >  4000 ? 0 : -1)));
-	}
-
-	ob = ee->ee_ob[ee_mode][obdb];
-	db = ee->ee_db[ee_mode][obdb];
-	x_gain = ee->ee_x_gain[ee_mode];
-	xpds = ee->ee_xpd[ee_mode];
-	xpdp = !xpds;
-
-	rf[11].rf_value[freq] = (rf[11].rf_value[freq] & ~0xc0) |
-		(((ath5k_hw_bitswap(x_gain, 4) << 7) | (xpdp << 6)) & 0xc0);
-	rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x7) |
-		((ath5k_hw_bitswap(x_gain, 4) >> 1) & 0x7);
-	rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x80) |
-		((ath5k_hw_bitswap(ob, 3) << 7) & 0x80);
-	rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x3) |
-		((ath5k_hw_bitswap(ob, 3) >> 1) & 0x3);
-	rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x1c) |
-		((ath5k_hw_bitswap(db, 3) << 2) & 0x1c);
-	rf[17].rf_value[freq] = (rf[17].rf_value[freq] & ~0x8) |
-		((xpds << 3) & 0x8);
-
-	for (i = 0; i < ARRAY_SIZE(rf); i++) {
-		AR5K_REG_WAIT(i);
-		ath5k_hw_reg_write(hal, rf[i].rf_value[freq],
-			(u32)rf[i].rf_register);
-	}
-
-	hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
-}
-
-bool
-ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq)
-{
-	unsigned int i;
-
-	switch (phy) {
-	case AR5K_INI_PHY_5111:
-	case AR5K_INI_PHY_5112:
+	switch (hal->ah_radio) {
+	case AR5K_RF5111:
+		ath5k_rfg = rf5111_ini_rfgain;
+		size = ARRAY_SIZE(rf5111_ini_rfgain);
 		break;
+	case AR5K_RF5112:
+		ath5k_rfg = rf5112_ini_rfgain;
+		size = ARRAY_SIZE(rf5112_ini_rfgain);
 	default:
-		return false;
+		return -EINVAL;
 	}
 
 	switch (freq) {
@@ -5347,16 +5327,16 @@ ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq)
 	case AR5K_INI_RFGAIN_5GHZ:
 		break;
 	default:
-		return false;
+		return -EINVAL;
 	}
 
-	for (i = 0; i < ARRAY_SIZE(ath5k_rfg); i++) {
+	for (i = 0; i < size; i++) {
 		AR5K_REG_WAIT(i);
-		ath5k_hw_reg_write(hal, ath5k_rfg[i].rfg_value[phy][freq],
+		ath5k_hw_reg_write(hal, ath5k_rfg[i].rfg_value[freq],
 			(u32)ath5k_rfg[i].rfg_register);
 	}
 
-	return true;
+	return 0;
 }
 
 enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal)

commit 9d5ff9cab00f80b019a73bfd8e4dcb40c17e703d
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Tue Aug 21 03:34:24 2007 +0200

    little whitespace

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 56f78d3..5f0aa32 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -344,7 +344,7 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc,
 	/*
 	 * Set the mac revision based on the pci id
 	 */
-	hal->ah_version	= mac_version;
+	hal->ah_version = mac_version;
 
 	/*Fill the hal struct with the needed functions*/
 	if (hal->ah_version == AR5K_AR5212)

commit 2f875dbedbd9d9cc0f106fd01f70d2332d890a08
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Wed Aug 8 21:49:23 2007 +0200

    fix some whitespace (checkpatch)

diff --git a/ath5k_hw.c b/ath5k_hw.c
index def9b8f..56f78d3 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -325,20 +325,20 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc,
 	hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
 
 	switch (device) {
-		case PCI_DEVICE_ID_ATHEROS_AR2413:
-		case PCI_DEVICE_ID_ATHEROS_AR5413:
-		case PCI_DEVICE_ID_ATHEROS_AR5424:
-			/*
-			 * Known single chip solutions
-			 */
-			hal->ah_single_chip = true;
-			break;
-		default:
-			/*
-			 * Multi chip solutions
-			 */
-			hal->ah_single_chip = false;
-			break;
+	case PCI_DEVICE_ID_ATHEROS_AR2413:
+	case PCI_DEVICE_ID_ATHEROS_AR5413:
+	case PCI_DEVICE_ID_ATHEROS_AR5424:
+		/*
+		 * Known single chip solutions
+		 */
+		hal->ah_single_chip = true;
+		break;
+	default:
+		/*
+		 * Multi chip solutions
+		 */
+		hal->ah_single_chip = false;
+		break;
 	}
 
 	/*
@@ -379,15 +379,16 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc,
 	hal->ah_mac_srev = srev;
 	hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
 	hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
-	hal->ah_phy_revision = ath5k_hw_reg_read(hal, AR5K_PHY_CHIP_ID) & 0x00ffffffff;
-	hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal,CHANNEL_5GHZ);
+	hal->ah_phy_revision = ath5k_hw_reg_read(hal, AR5K_PHY_CHIP_ID) &
+			0xffffffff;
+	hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal,
+			CHANNEL_5GHZ);
 
-	if (hal->ah_version == AR5K_AR5210) {
+	if (hal->ah_version == AR5K_AR5210)
 		hal->ah_radio_2ghz_revision = 0;
-	} else {
+	else
 		hal->ah_radio_2ghz_revision = ath5k_hw_radio_revision(hal,
 				CHANNEL_2GHZ);
-	}
 
 	/* Single chip radio */
 	if (hal->ah_radio_2ghz_revision == hal->ah_radio_5ghz_revision)
@@ -511,11 +512,10 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial)
 			mode |= AR5K_PHY_MODE_MOD_CCK;
 		} else if (flags & CHANNEL_G) {
 			/* Dynamic OFDM/CCK is not supported by the AR5211 */
-			if (hal->ah_version == AR5K_AR5211) {
+			if (hal->ah_version == AR5K_AR5211)
 				mode |= AR5K_PHY_MODE_MOD_CCK;
-			} else {
+			else
 				mode |= AR5K_PHY_MODE_MOD_DYN;
-			}
 		} else if (flags & CHANNEL_OFDM) {
 			mode |= AR5K_PHY_MODE_MOD_OFDM;
 		} else {
@@ -523,17 +523,9 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial)
 			return -EINVAL;
 		}
 
-		if (flags & CHANNEL_TURBO) {
-			turbo = AR5K_PHY_TURBO_MODE |
-			    AR5K_PHY_TURBO_SHORT;
-		}
-	}
-
-	/*
-	 * Reset and wakeup the device
-	 */
-
-	else {
+		if (flags & CHANNEL_TURBO)
+			turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
+	} else { /* Reset and wakeup the device */
 		if (initial == true) {
 			/* ...reset hardware */
 			if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_PCI)) {
@@ -553,7 +545,8 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial)
 
 		/* ...enable Atheros turbo mode if requested */
 		if (flags & CHANNEL_TURBO)
-			ath5k_hw_reg_write(hal, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO);
+			ath5k_hw_reg_write(hal, AR5K_PHY_TURBO_MODE,
+					AR5K_PHY_TURBO);
 
 		/* ...reset chipset */
 		if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP)) {
@@ -587,7 +580,7 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial)
 		return -EIO;
 	}
 
-	if (hal->ah_version != AR5K_AR5210){
+	if (hal->ah_version != AR5K_AR5210) {
 		/* ...set the PHY operating mode */
 		ath5k_hw_reg_write(hal, clock, AR5K_PHY_PLL);
 		udelay(300);
@@ -637,7 +630,8 @@ static u16 ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan)
 		ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
 	} else {
 		srev = (ath5k_hw_reg_read(hal, AR5K_PHY(0x100)) >> 24) & 0xff;
-		ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8);
+		ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
+				((srev & 0x0f) << 4), 8);
 	}
 
 	/* Reset to the 5GHz mode */
@@ -721,15 +715,16 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 	/*DCU/Antenna selection not available on 5210*/
 	if (hal->ah_version != AR5K_AR5210) {
 		if (change_channel == true) {
-			/*Sequence number for queue 0 -do this for all queues ?*/
-			s_seq = ath5k_hw_reg_read(hal, AR5K_QUEUE_DFS_SEQNUM(0));
+			/* Seq number for queue 0 -do this for all queues ? */
+			s_seq = ath5k_hw_reg_read(hal,
+					AR5K_QUEUE_DFS_SEQNUM(0));
 			/*Default antenna*/
 			s_ant = ath5k_hw_reg_read(hal, AR5K_DEFAULT_ANTENNA);
 		}
 	}
 
 	/*GPIOs*/
-	s_led[0] = ath5k_hw_reg_read(hal, AR5K_PCICFG) &	AR5K_PCICFG_LEDSTATE;
+	s_led[0] = ath5k_hw_reg_read(hal, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE;
 	s_led[1] = ath5k_hw_reg_read(hal, AR5K_GPIOCR);
 	s_led[2] = ath5k_hw_reg_read(hal, AR5K_GPIODO);
 
@@ -807,7 +802,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 
 		/*
 		 * Write initial RF registers on 5211
-		 * do we need that ? Is ath5k_hw_rfregs going to work for 5211 (5111) ?
+		 * do we need that ? Is ath5k_hw_rfregs going to work for
+		 * 5211 (5111) ?
 		 */
 		if (hal->ah_version == AR5K_AR5211)
 			ath5k_hw_ar5211_rfregs(hal, channel, freq, ee_mode);
@@ -822,11 +818,11 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 		for (i = 0; i < ARRAY_SIZE(ar5212_mode); i++) {
 			if (ar5212_mode[i].mode_flags == AR5K_INI_FLAG_511X)
 				off = AR5K_INI_PHY_511X;
-			else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5111 &&
-			    hal->ah_radio == AR5K_RF5111)
+			else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5111
+					&& hal->ah_radio == AR5K_RF5111)
 				off = AR5K_INI_PHY_5111;
-			else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5112 &&
-			    hal->ah_radio == AR5K_RF5112)
+			else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5112
+					&& hal->ah_radio == AR5K_RF5112)
 				off = AR5K_INI_PHY_5112;
 			else
 				continue;
@@ -888,9 +884,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 		 * Write initial RF gain settings
 		 * This should work for both 5111/5112
 		 */
-		if (ath5k_hw_rfgain(hal, phy, freq) == false) {
+		if (ath5k_hw_rfgain(hal, phy, freq) == false)
 			return -EIO;
-		}
 
 		mdelay(1);
 
@@ -913,37 +908,38 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 						ath_hal_computetxtime(hal, rt,
 						14, rt->rates[i].control_rate,
 						false), data);
-					if (HAS_SHPREAMBLE(i)) {
+					if (HAS_SHPREAMBLE(i))
 						ath5k_hw_reg_write(hal,
-						    ath_hal_computetxtime(hal, rt, 14,
-						    rt->rates[i].control_rate, false),
-						    data +
+						    ath_hal_computetxtime(hal,
+						    rt, 14,
+						    rt->rates[i].control_rate,
+						    false), data +
 						    (AR5K_SET_SHORT_PREAMBLE << 2));
-					}
 				}
 
 			} else {
-			/*For 802.11a/g Turbo/XR mode (AR5K_MODE_XR here is O.K. for both a/g - OFDM)*/
+			/* For 802.11a/g Turbo/XR mode (AR5K_MODE_XR here is
+			 * O.K. for both a/g - OFDM) */
 
-				/*Get rate table for this operation mode*/
+				/* Get rate table for this operation mode */
 				rt = ath5k_hw_get_rate_table(hal,
 				    channel->val & CHANNEL_TURBO ?
 				    MODE_ATHEROS_TURBO : MODE_ATHEROS_TURBOG);
 
-				/*Write rate duration table*/
-				for (i = 0; i < rt->rate_count; i++) {
+				/* Write rate duration table */
+				for (i = 0; i < rt->rate_count; i++)
 					ath5k_hw_reg_write(hal,
 						ath_hal_computetxtime(hal, rt,
 						14, rt->rates[i].control_rate,
 						false),
 						AR5K_RATE_DUR(rt->rates[i].rate_code));
-				}
 
 			}
 		}
 
 		/* Fix for first revision of the RF5112 RF chipset */
-		if (hal->ah_radio >= AR5K_RF5112 && hal->ah_radio_5ghz_revision<
+		if (hal->ah_radio >= AR5K_RF5112 &&
+				hal->ah_radio_5ghz_revision <
 				AR5K_SREV_RAD_5112A) {
 			ath5k_hw_reg_write(hal, AR5K_PHY_CCKTXCTL_WORLD,
 					AR5K_PHY_CCKTXCTL);
@@ -976,22 +972,23 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 		/* Write OFDM timings on 5212*/
 		if (hal->ah_version == AR5K_AR5212) {
 			if (channel->val & CHANNEL_OFDM) {
-				u32 coef_scaled, coef_exp, coef_man, ds_coef_exp,
-				    ds_coef_man, clock;
+				u32 coef_scaled, coef_exp, coef_man,
+					ds_coef_exp, ds_coef_man, clock;
 
 				clock = channel->val & CHANNEL_T ? 80 : 40;
-				coef_scaled = ((5 * (clock << 24)) / 2) / channel->freq;
+				coef_scaled = ((5 * (clock << 24)) / 2) /
+					channel->freq;
 
 				for (coef_exp = 31; coef_exp > 0; coef_exp--)
 					if ((coef_scaled >> coef_exp) & 0x1)
 						break;
 
-				if (!coef_exp) {
+				if (!coef_exp)
 					return -EINVAL;
-				}
 
 				coef_exp = 14 - (coef_exp - 24);
-				coef_man = coef_scaled + (1 << (24 - coef_exp - 1));
+				coef_man = coef_scaled +
+					(1 << (24 - coef_exp - 1));
 				ds_coef_man = coef_man >> (24 - coef_exp);
 				ds_coef_exp = coef_exp - 16;
 
@@ -1037,12 +1034,15 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 			AR5K_PHY(0x5a));
 
 		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x11),
-		    (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f);
+			(ee->ee_switch_settling[ee_mode] << 7) & 0x3f80,
+			0xffffc07f);
 		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x12),
-		    (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff);
+			(ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000,
+			0xfffc0fff);
 		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x14),
-		    (ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
-		    ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000);
+			(ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
+			((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00),
+			0xffff0000);
 
 		ath5k_hw_reg_write(hal,
 			(ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
@@ -1051,9 +1051,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 			(ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d));
 
 		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x0a),
-		    ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
+			ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
 		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x19),
-		    (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
+			(ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
 		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x49), 4, 0xffffff01);
 
 		AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ,
@@ -1061,11 +1061,10 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 		    (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
 		    ee->ee_q_cal[ee_mode]);
 
-		if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
+		if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
 			AR5K_REG_WRITE_BITS(hal, AR5K_PHY_GAIN_2GHZ,
 				AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
 				ee->ee_margin_tx_rx[ee_mode]);
-		}
 
 	} else {
 		mdelay(1);
@@ -1131,9 +1130,10 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 	 * 5111/5112 Specific
 	 */
 	if (hal->ah_version != AR5K_AR5210) {
-		data = ath5k_hw_reg_read(hal, AR5K_PHY_RX_DELAY) & AR5K_PHY_RX_DELAY_M;
+		data = ath5k_hw_reg_read(hal, AR5K_PHY_RX_DELAY) &
+			AR5K_PHY_RX_DELAY_M;
 		data = (channel->val & CHANNEL_CCK) ?
-		    ((data << 2) / 22) : (data / 10);
+			((data << 2) / 22) : (data / 10);
 
 		udelay(100 + data);
 	} else {
@@ -1210,9 +1210,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 	}
 
 	/* Pre-enable interrupts on 5211/5212*/
-	if (hal->ah_version != AR5K_AR5210) {
-		ath5k_hw_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_FATAL);
-	}
+	if (hal->ah_version != AR5K_AR5210)
+		ath5k_hw_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX |
+				AR5K_INT_FATAL);
 
 	/*
 	 * Set RF kill flags if supported by the device (read from the EEPROM)
@@ -1222,7 +1222,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 #if 0
 	if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) {
 		ath5k_hw_set_gpio_input(hal, 0);
-		if ((hal->ah_gpio[0] = ath5k_hw_get_gpio(hal, 0)) == 0)
+		hal->ah_gpio[0] = ath5k_hw_get_gpio(hal, 0);
+		if (hal->ah_gpio[0] == 0)
 			ath5k_hw_set_gpio_intr(hal, 0, 1);
 		else
 			ath5k_hw_set_gpio_intr(hal, 0, 0);
@@ -1313,19 +1314,19 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode,
 		staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
 		/* fallthrough */
 	case AR5K_PM_NETWORK_SLEEP:
-		if (set_chip == true) {
+		if (set_chip == true)
 			ath5k_hw_reg_write(hal,
 				AR5K_SLEEP_CTL_SLE | sleep_duration,
 				AR5K_SLEEP_CTL);
-		}
+
 		staid |= AR5K_STA_ID1_PWR_SV;
 		break;
 
 	case AR5K_PM_FULL_SLEEP:
-		if (set_chip == true) {
+		if (set_chip == true)
 			ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_SLP,
 				AR5K_SLEEP_CTL);
-		}
+
 		staid |= AR5K_STA_ID1_PWR_SV;
 		break;
 
@@ -1333,7 +1334,8 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode,
 		if (set_chip == false)
 			goto commit;
 
-		ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_WAKE, AR5K_SLEEP_CTL);
+		ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_WAKE,
+				AR5K_SLEEP_CTL);
 
 		for (i = 5000; i > 0; i--) {
 			/* Check if the chip did wake up */
@@ -1460,22 +1462,21 @@ int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue)
 		 * Set the queue by type on 5210
 		 */
 		switch (hal->ah_txq[queue].tqi_type) {
-			case AR5K_TX_QUEUE_DATA:
-				tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
-				break;
-			case AR5K_TX_QUEUE_BEACON:
-				tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
-				ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V |
-					AR5K_BCR_BDMAE, AR5K_BSR);
-				break;
-			case AR5K_TX_QUEUE_CAB:
-				tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
-				ath5k_hw_reg_write(hal, AR5K_BCR_TQ1FV |
-					AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
+		case AR5K_TX_QUEUE_DATA:
+			tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
+			break;
+		case AR5K_TX_QUEUE_BEACON:
+			tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
+			ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
 					AR5K_BSR);
-				break;
-			default:
-				return -EINVAL;
+			break;
+		case AR5K_TX_QUEUE_CAB:
+			tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
+			ath5k_hw_reg_write(hal, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V |
+				AR5K_BCR_BDMAE, AR5K_BSR);
+			break;
+		default:
+			return -EINVAL;
 		}
 		/* Start queue */
 		ath5k_hw_reg_write(hal, tx_queue, AR5K_CR);
@@ -1515,17 +1516,17 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue)
 		 * Set by queue type
 		 */
 		switch (hal->ah_txq[queue].tqi_type) {
-			case AR5K_TX_QUEUE_DATA:
-				tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
-				break;
-			case AR5K_TX_QUEUE_BEACON:
-			case AR5K_TX_QUEUE_CAB:
-				/* XXX Fix me... */
-				tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1;
-				ath5k_hw_reg_write(hal, 0, AR5K_BSR);
-				break;
-			default:
-				return false;
+		case AR5K_TX_QUEUE_DATA:
+			tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
+			break;
+		case AR5K_TX_QUEUE_BEACON:
+		case AR5K_TX_QUEUE_CAB:
+			/* XXX Fix me... */
+			tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1;
+			ath5k_hw_reg_write(hal, 0, AR5K_BSR);
+			break;
+		default:
+			return false;
 		}
 
 		/* Stop queue */
@@ -1538,8 +1539,9 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue)
 
 		/*Check for pending frames*/
 		do {
-			pending = ath5k_hw_reg_read(hal, AR5K_QUEUE_STATUS(queue)) &
-						AR5K_QCU_STS_FRMPENDCNT;
+			pending = ath5k_hw_reg_read(hal,
+				AR5K_QUEUE_STATUS(queue)) &
+				AR5K_QCU_STS_FRMPENDCNT;
 			udelay(100);
 		} while (--i && pending);
 
@@ -1547,7 +1549,7 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue)
 		ath5k_hw_reg_write(hal, 0, AR5K_QCU_TXD);
 	}
 
-	/*TODO: Check for success else return false*/
+	/* TODO: Check for success else return false */
 	return true;
 }
 
@@ -1568,15 +1570,15 @@ u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue)
 	/*5210 doesn't have QCU*/
 	if (hal->ah_version == AR5K_AR5210) {
 		switch (hal->ah_txq[queue].tqi_type) {
-			case AR5K_TX_QUEUE_DATA:
-				tx_reg = AR5K_NOQCU_TXDP0;
-				break;
-			case AR5K_TX_QUEUE_BEACON:
-			case AR5K_TX_QUEUE_CAB:
-				tx_reg = AR5K_NOQCU_TXDP1;
-				break;
-			default:
-				return 0xffffffff;
+		case AR5K_TX_QUEUE_DATA:
+			tx_reg = AR5K_NOQCU_TXDP0;
+			break;
+		case AR5K_TX_QUEUE_BEACON:
+		case AR5K_TX_QUEUE_CAB:
+			tx_reg = AR5K_NOQCU_TXDP1;
+			break;
+		default:
+			return 0xffffffff;
 		}
 	} else {
 		tx_reg = AR5K_QUEUE_TXDP(queue);
@@ -1602,15 +1604,15 @@ int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr)
 	 */
 	if (hal->ah_version == AR5K_AR5210) {
 		switch (hal->ah_txq[queue].tqi_type) {
-			case AR5K_TX_QUEUE_DATA:
-				tx_reg = AR5K_NOQCU_TXDP0;
-				break;
-			case AR5K_TX_QUEUE_BEACON:
-			case AR5K_TX_QUEUE_CAB:
-				tx_reg = AR5K_NOQCU_TXDP1;
-				break;
-			default:
-				return -EINVAL;
+		case AR5K_TX_QUEUE_DATA:
+			tx_reg = AR5K_NOQCU_TXDP0;
+			break;
+		case AR5K_TX_QUEUE_BEACON:
+		case AR5K_TX_QUEUE_CAB:
+			tx_reg = AR5K_NOQCU_TXDP1;
+			break;
+		default:
+			return -EINVAL;
 		}
 	} else {
 		/*
@@ -1908,7 +1910,8 @@ static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data)
 	if (hal->ah_version == AR5K_AR5210) {
 		AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_EEAE);
 	} else {
-		AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_RESET);
+		AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD,
+				AR5K_EEPROM_CMD_RESET);
 	}
 
 	/*
@@ -1920,7 +1923,8 @@ static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data)
 	} else {
 		ath5k_hw_reg_write(hal, offset, AR5K_EEPROM_BASE);
 		ath5k_hw_reg_write(hal, data, AR5K_EEPROM_DATA);
-		AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_WRITE);
+		AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD,
+				AR5K_EEPROM_CMD_WRITE);
 	}
 
 	/*
@@ -2185,7 +2189,8 @@ static int ath5k_eeprom_init(struct ath_hw *hal)
 	 */
 	mode = AR5K_EEPROM_MODE_11A;
 
-	ee->ee_turbo_max_power[mode] = AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
+	ee->ee_turbo_max_power[mode] =
+			AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
 
 	offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version);
 
@@ -2247,9 +2252,8 @@ static int ath5k_eeprom_init(struct ath_hw *hal)
 			ath5k_eeprom_bin2freq(hal, val & 0xff, mode);
 	}
 
-	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
+	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
 		ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
-	}
 
 	/*
 	 * Get values for 802.11g (2.4GHz)
@@ -2412,12 +2416,13 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal)
 	} else {
 		/*
 		 * XXX The tranceiver supports frequencies from 4920 to 6100GHz
-		 * XXX and from 2312 to 2732GHz. There are problems with the current
-		 * XXX ieee80211 implementation because the IEEE channel mapping
-		 * XXX does not support negative channel numbers (2312MHz is channel
-		 * XXX -19). Of course, this doesn't matter because these channels
-		 * XXX are out of range but some regulation domains like MKK (Japan)
-		 * XXX will support frequencies somewhere around 4.8GHz.
+		 * XXX and from 2312 to 2732GHz. There are problems with the
+		 * XXX current ieee80211 implementation because the IEEE
+		 * XXX channel mapping does not support negative channel
+		 * XXX numbers (2312MHz is channel -19). Of course, this
+		 * XXX doesn't matter because these channels are out of range
+		 * XXX but some regulation domains like MKK (Japan) will
+		 * XXX support frequencies somewhere around 4.8GHz.
 		 */
 
 		/*
@@ -2437,8 +2442,10 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal)
 						hal->ah_capabilities.cap_mode);
 		}
 
-		/* Enable  802.11b if a 2GHz capable radio (2111/5112) is connected */
-		if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) {
+		/* Enable  802.11b if a 2GHz capable radio (2111/5112) is
+		 * connected */
+		if (AR5K_EEPROM_HDR_11B(ee_header) ||
+				AR5K_EEPROM_HDR_11G(ee_header)) {
 			hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
 			hal->ah_capabilities.cap_range.range_2ghz_max = 2732;
 
@@ -2457,7 +2464,8 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal)
 
 	/* Set number of supported TX queues */
 	if (hal->ah_version == AR5K_AR5210)
-		hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES_NOQCU;
+		hal->ah_capabilities.cap_queues.q_tx_num =
+			AR5K_NUM_TX_QUEUES_NOQCU;
 	else
 		hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
 
@@ -2601,7 +2609,7 @@ ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id)
  * Set BSSID mask on 5212
  */
 bool
-ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask)
+ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8 *mask)
 {
 	u32 low_id, high_id;
 	AR5K_TRACE;
@@ -2844,7 +2852,8 @@ void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32 interval)
  * Set beacon timers
  */
 void
-ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *state)
+ath5k_hw_set_beacon_timers(struct ath_hw *hal,
+		const struct ath5k_beacon_state *state)
 {
 	u32 cfp_period, next_cfp, dtim, interval, next_beacon;
 
@@ -2885,7 +2894,8 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *
 				AR5K_STA_ID1_DEFAULT_ANTENNA |
 				AR5K_STA_ID1_PCF);
 		ath5k_hw_reg_write(hal, cfp_period, AR5K_CFP_PERIOD);
-		ath5k_hw_reg_write(hal, state->bs_cfp_max_duration, AR5K_CFP_DUR);
+		ath5k_hw_reg_write(hal, state->bs_cfp_max_duration,
+				AR5K_CFP_DUR);
 		ath5k_hw_reg_write(hal, (tsf + (next_cfp == 0 ? cfp_period :
 						next_cfp)) << 3, AR5K_TIMER2);
 	} else {
@@ -3039,7 +3049,8 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr)
  * Update mib counters (statistics)
  */
 void
-ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics)
+ath5k_hw_update_mib_counters(struct ath_hw *hal,
+		struct ath5k_mib_stats *statistics)
 {
 	AR5K_TRACE;
 	/* Read-And-Clear */
@@ -3240,44 +3251,44 @@ int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type,
 	/*5210 only has 2 queues*/
 	if (hal->ah_version == AR5K_AR5210) {
 		switch (queue_type) {
-			case AR5K_TX_QUEUE_DATA:
-				queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
-				break;
-			case AR5K_TX_QUEUE_BEACON:
-			case AR5K_TX_QUEUE_CAB:
-				queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
-				break;
-			default:
-				return -EINVAL;
+		case AR5K_TX_QUEUE_DATA:
+			queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
+			break;
+		case AR5K_TX_QUEUE_BEACON:
+		case AR5K_TX_QUEUE_CAB:
+			queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
+			break;
+		default:
+			return -EINVAL;
 		}
 	} else {
 		switch (queue_type) {
-			case AR5K_TX_QUEUE_DATA:
-				for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
-					hal->ah_txq[queue].tqi_type !=
-					AR5K_TX_QUEUE_INACTIVE; queue++) {
+		case AR5K_TX_QUEUE_DATA:
+			for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
+				hal->ah_txq[queue].tqi_type !=
+				AR5K_TX_QUEUE_INACTIVE; queue++) {
 
-					if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
-						return -EINVAL;
-				}
-				break;
-			case AR5K_TX_QUEUE_UAPSD:
-				queue = AR5K_TX_QUEUE_ID_UAPSD;
-				break;
-			case AR5K_TX_QUEUE_BEACON:
-				queue = AR5K_TX_QUEUE_ID_BEACON;
-				break;
-			case AR5K_TX_QUEUE_CAB:
-				queue = AR5K_TX_QUEUE_ID_CAB;
-				break;
-			case AR5K_TX_QUEUE_XR_DATA:
-				if (hal->ah_version != AR5K_AR5212)
-					AR5K_PRINTF("XR data queues only "
-							"supported in 5212!\n");
-				queue = AR5K_TX_QUEUE_ID_XR_DATA;
-				break;
-			default:
-				return -EINVAL;
+				if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
+					return -EINVAL;
+			}
+			break;
+		case AR5K_TX_QUEUE_UAPSD:
+			queue = AR5K_TX_QUEUE_ID_UAPSD;
+			break;
+		case AR5K_TX_QUEUE_BEACON:
+			queue = AR5K_TX_QUEUE_ID_BEACON;
+			break;
+		case AR5K_TX_QUEUE_CAB:
+			queue = AR5K_TX_QUEUE_ID_CAB;
+			break;
+		case AR5K_TX_QUEUE_XR_DATA:
+			if (hal->ah_version != AR5K_AR5212)
+				AR5K_PRINTF("XR data queues only supported in "
+						"5212!\n");
+			queue = AR5K_TX_QUEUE_ID_XR_DATA;
+			break;
+		default:
+			return -EINVAL;
 		}
 	}
 
@@ -3461,7 +3472,8 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 			AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
 			AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
 			AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs,
-			AR5K_DCU_LCL_IFS_AIFS), AR5K_QUEUE_DFS_LOCAL_IFS(queue));
+				AR5K_DCU_LCL_IFS_AIFS),
+			AR5K_QUEUE_DFS_LOCAL_IFS(queue));
 
 		/*
 		 * Set misc registers
@@ -3483,12 +3495,11 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 					AR5K_QCU_MISC_CBR_THRES_ENABLE);
 		}
 
-		if (tq->tqi_ready_time) {
+		if (tq->tqi_ready_time)
 			ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_ready_time,
 				AR5K_QCU_RDYTIMECFG_INTVAL) |
 				AR5K_QCU_RDYTIMECFG_ENABLE,
 				AR5K_QUEUE_RDYTIMECFG(queue));
-		}
 
 		if (tq->tqi_burst_time) {
 			ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_burst_time,
@@ -3496,48 +3507,43 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 				AR5K_DCU_CHAN_TIME_ENABLE,
 				AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
 
-			if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) {
-				AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue),
+			if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
+				AR5K_REG_ENABLE_BITS(hal,
+					AR5K_QUEUE_MISC(queue),
 					AR5K_QCU_MISC_TXE);
-			}
 		}
 
-		if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) {
+		if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
 			ath5k_hw_reg_write(hal, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
 				AR5K_QUEUE_DFS_MISC(queue));
-		}
 
-		if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
+		if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
 			ath5k_hw_reg_write(hal, AR5K_DCU_MISC_BACKOFF_FRAG,
 				AR5K_QUEUE_DFS_MISC(queue));
-		}
 
 		/*
 		 * Set registers by queue type
 		 */
 		switch (tq->tqi_type) {
-			case AR5K_TX_QUEUE_BEACON:
-				AR5K_REG_ENABLE_BITS(hal,
-					AR5K_QUEUE_MISC(queue),
-					AR5K_QCU_MISC_FRSHED_DBA_GT |
-					AR5K_QCU_MISC_CBREXP_BCN |
-					AR5K_QCU_MISC_BCN_ENABLE);
+		case AR5K_TX_QUEUE_BEACON:
+			AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue),
+				AR5K_QCU_MISC_FRSHED_DBA_GT |
+				AR5K_QCU_MISC_CBREXP_BCN |
+				AR5K_QCU_MISC_BCN_ENABLE);
 
-				AR5K_REG_ENABLE_BITS(hal,
-					AR5K_QUEUE_DFS_MISC(queue),
-					(AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
-					AR5K_DCU_MISC_ARBLOCK_CTL_S) |
-					AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
-					AR5K_DCU_MISC_BCN_ENABLE);
-
-				ath5k_hw_reg_write(hal,
-					((AR5K_TUNE_BEACON_INTERVAL -
-					(AR5K_TUNE_SW_BEACON_RESP -
-					AR5K_TUNE_DMA_BEACON_RESP) -
-					AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
-					AR5K_QCU_RDYTIMECFG_ENABLE,
-					AR5K_QUEUE_RDYTIMECFG(queue));
-				break;
+			AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_DFS_MISC(queue),
+				(AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
+				AR5K_DCU_MISC_ARBLOCK_CTL_S) |
+				AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
+				AR5K_DCU_MISC_BCN_ENABLE);
+
+			ath5k_hw_reg_write(hal, ((AR5K_TUNE_BEACON_INTERVAL -
+				(AR5K_TUNE_SW_BEACON_RESP -
+				AR5K_TUNE_DMA_BEACON_RESP) -
+				AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
+				AR5K_QCU_RDYTIMECFG_ENABLE,
+				AR5K_QUEUE_RDYTIMECFG(queue));
+			break;
 
 		case AR5K_TX_QUEUE_CAB:
 			AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue),
@@ -3650,8 +3656,8 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc,
 {
 	u32 frame_type;
 	struct ath5k_hw_2w_tx_desc *tx_desc;
-
-	tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0;
+	
+	tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0;
 
 	if (tx_tries0 == 0)
 		return -EINVAL;
@@ -3671,7 +3677,8 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc,
 	 * XXX: I only found that on 5210 code, does it work on 5211 ?
 	 */
 	if (hal->ah_version == AR5K_AR5210) {
-		tx_desc->tx_control_0 = hdr_len & AR5K_2W_TX_DESC_CTL0_HEADER_LEN;
+		tx_desc->tx_control_0 = hdr_len &
+				AR5K_2W_TX_DESC_CTL0_HEADER_LEN;
 		if (tx_desc->tx_control_0 != hdr_len)
 			return -EINVAL;
 	}
@@ -3679,17 +3686,17 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc,
 	/*Diferences between 5210-5211*/
 	if (hal->ah_version == AR5K_AR5210) {
 		switch (type) {
-			case AR5K_PKT_TYPE_BEACON:
-			case AR5K_PKT_TYPE_PROBE_RESP:
-				frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
-			case AR5K_PKT_TYPE_PIFS:
-				frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
-			default:
-				frame_type = type /*<< 2 ?*/;
+		case AR5K_PKT_TYPE_BEACON:
+		case AR5K_PKT_TYPE_PROBE_RESP:
+			frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
+		case AR5K_PKT_TYPE_PIFS:
+			frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
+		default:
+			frame_type = type /*<< 2 ?*/;
 		}
 
 		tx_desc->tx_control_0 =
-			AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE)|
+			AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
 			AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
 	} else {
 		tx_desc->tx_control_0 |=
@@ -3726,10 +3733,9 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc,
 	 * RTS/CTS Duration [5210 ?]
 	 */
 	if ((hal->ah_version == AR5K_AR5210) &&
-			(flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA))) {
-		tx_desc->tx_control_1 |=
-			rtscts_duration & AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
-	}
+			(flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
+		tx_desc->tx_control_1 |= rtscts_duration &
+				AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
 
 	return 0;
 }
@@ -3748,7 +3754,7 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal,
 
 	AR5K_TRACE;
 
-	tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0;
+	tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
 
 	/*
 	 * Validate input
@@ -3803,7 +3809,8 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal,
 	 * RTS/CTS
 	 */
 	if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
-		if ((flags & AR5K_TXDESC_RTSENA) &&(flags & AR5K_TXDESC_CTSENA))
+		if ((flags & AR5K_TXDESC_RTSENA) &&
+				(flags & AR5K_TXDESC_CTSENA))
 			return -EINVAL;
 		tx_desc->tx_control_2 |= rtscts_duration &
 				AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
@@ -3825,7 +3832,7 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hw *hal, struct ath_desc *desc,
 	struct ath5k_hw_4w_tx_desc *tx_desc;
 
 	if (hal->ah_version == AR5K_AR5212) {
-		tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0;
+		tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
 
 #define _XTX_TRIES(_n)							\
 	if (tx_tries##_n) {						\
@@ -3846,7 +3853,7 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hw *hal, struct ath_desc *desc,
 		return true;
 	}
 
-	return(false);
+	return false;
 }
 
 /*
@@ -3858,7 +3865,7 @@ static int ath5k_hw_fill_2word_tx_desc(struct ath_hw *hal,
 {
 	struct ath5k_hw_2w_tx_desc *tx_desc;
 
-	tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0;
+	tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0;
 
 	/* Clear status descriptor */
 	memset(desc->ds_hw, 0, sizeof(desc->ds_hw));
@@ -3889,8 +3896,8 @@ static int ath5k_hw_fill_4word_tx_desc(struct ath_hw *hal,
 	struct ath5k_hw_tx_status *tx_status;
 
 	AR5K_TRACE;
-	tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0;
-	tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2];
+	tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
+	tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2];
 
 	/* Clear status descriptor */
 	memset(tx_status, 0, sizeof(struct ath5k_hw_tx_status));
@@ -3918,8 +3925,8 @@ static int ath5k_hw_proc_2word_tx_status(struct ath_hw *hal,
 	struct ath5k_hw_tx_status *tx_status;
 	struct ath5k_hw_2w_tx_desc *tx_desc;
 
-	tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0;
-	tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[0];
+	tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0;
+	tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[0];
 
 	/* No frame has been send or error */
 	if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
@@ -3969,8 +3976,8 @@ static int ath5k_hw_proc_4word_tx_status(struct ath_hw *hal,
 	struct ath5k_hw_4w_tx_desc *tx_desc;
 
 	AR5K_TRACE;
-	tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0;
-	tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2];
+	tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
+	tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2];
 
 	/* No frame has been send or error */
 	if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
@@ -4047,7 +4054,7 @@ int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc,
 	struct ath5k_rx_desc *rx_desc;
 
 	AR5K_TRACE;
-	rx_desc = (struct ath5k_rx_desc*)&desc->ds_ctl0;
+	rx_desc = (struct ath5k_rx_desc *)&desc->ds_ctl0;
 
 	/*
 	 *Clear ds_hw
@@ -4081,7 +4088,7 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal,
 {
 	struct ath5k_hw_old_rx_status *rx_status;
 
-	rx_status = (struct ath5k_hw_old_rx_status*)&desc->ds_hw[0];
+	rx_status = (struct ath5k_hw_old_rx_status *)&desc->ds_hw[0];
 
 	/* No frame received / not ready */
 	if (unlikely((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE)
@@ -4094,15 +4101,15 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal,
 	desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
 		AR5K_OLD_RX_DESC_STATUS0_DATA_LEN;
 	desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
-	    	AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL);
+		AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL);
 	desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
-	    	AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE);
+		AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE);
 	desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
 		AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA;
 	desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
 		AR5K_OLD_RX_DESC_STATUS0_MORE;
 	desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
-	    	AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
+		AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
 	desc->ds_us.rx.rs_status = 0;
 
 	/*
@@ -4110,7 +4117,7 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal,
 	 */
 	if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID)
 		desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
-		    	AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX);
+			AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX);
 	else
 		desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID;
 
@@ -4152,10 +4159,10 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal,
 	struct ath5k_hw_rx_error *rx_err;
 
 	AR5K_TRACE;
-	rx_status = (struct ath5k_hw_new_rx_status*)&desc->ds_hw[0];
+	rx_status = (struct ath5k_hw_new_rx_status *)&desc->ds_hw[0];
 
 	/* Overlay on error */
-	rx_err = (struct ath5k_hw_rx_error*)&desc->ds_hw[0];
+	rx_err = (struct ath5k_hw_rx_error *)&desc->ds_hw[0];
 
 	/* No frame received / not ready */
 	if (unlikely((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE)
@@ -4196,7 +4203,8 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal,
 		if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR)
 			desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC;
 
-		if (rx_status->rx_status_1 &AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR){
+		if (rx_status->rx_status_1 &
+				AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR) {
 			desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY;
 			desc->ds_us.rx.rs_phyerr =
 				AR5K_REG_MS(rx_err->rx_error_1,
@@ -4516,12 +4524,12 @@ static int ath5k_hw_rf5111_channel(struct ath_hw *hal,
 
 	if (ath_channel < 145 || !(ath_channel & 1)) {
 		clock = 1;
-		data1 = ((ath5k_hw_bitswap(ath_channel - 24, 8) & 0xff) << 2)
-		    | (clock << 1) | (1 << 10) | 1;
+		data1 = ((ath5k_hw_bitswap(ath_channel - 24, 8) & 0xff) << 2) |
+			(clock << 1) | (1 << 10) | 1;
 	} else {
 		clock = 0;
-		data1 = ((ath5k_hw_bitswap((ath_channel - 24) / 2, 8) & 0xff) << 2)
-		    | (clock << 1) | (1 << 10) | 1;
+		data1 = ((ath5k_hw_bitswap((ath_channel - 24) / 2, 8) & 0xff)
+			<< 2) | (clock << 1) | (1 << 10) | 1;
 	}
 
 	ath5k_hw_reg_write(hal, (data1 & 0xff) | ((data0 & 0xff) << 8),
@@ -4985,11 +4993,10 @@ static s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal)
 				hal->ah_gain.g_target >=  hal->ah_gain.g_high &&
 				hal->ah_gain.g_step_idx > 0;
 				hal->ah_gain.g_step =
-					&go->go_step[hal->ah_gain.g_step_idx]) {
+					&go->go_step[hal->ah_gain.g_step_idx])
 			hal->ah_gain.g_target -= 2 *
 			    (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain -
 			    hal->ah_gain.g_step->gos_gain);
-		}
 
 		ret = 1;
 		goto done;
@@ -5002,11 +5009,10 @@ static s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal)
 				hal->ah_gain.g_target <= hal->ah_gain.g_low &&
 				hal->ah_gain.g_step_idx < go->go_steps_count-1;
 				hal->ah_gain.g_step =
-					&go->go_step[hal->ah_gain.g_step_idx]) {
+					&go->go_step[hal->ah_gain.g_step_idx])
 			hal->ah_gain.g_target -= 2 *
 			    (go->go_step[++hal->ah_gain.g_step_idx].gos_gain -
 			    hal->ah_gain.g_step->gos_gain);
-		}
 
 		ret = 2;
 		goto done;
@@ -5484,13 +5490,12 @@ ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel,
 		AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
 		AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
 
-	if (hal->ah_txpower.txp_tpc == true) {
+	if (hal->ah_txpower.txp_tpc == true)
 		ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
 			AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
-	} else {
+	else
 		ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX |
 			AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
-	}
 
 	return 0;
 }
@@ -5502,7 +5507,7 @@ int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power)
 
 	AR5K_TRACE;
 #ifdef AR5K_DEBUG
-	AR5K_PRINTF("changing txpower to %d\n",power);
+	AR5K_PRINTF("changing txpower to %d\n", power);
 #endif
 	return ath5k_hw_txpower(hal, channel, power);
 }

commit 57ba7c06221ec54c1c91f04582d71332879076c0
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Tue Aug 7 08:19:20 2007 +0200

    remove sp[ace on the line beginning

diff --git a/ath5k_hw.c b/ath5k_hw.c
index ba76103..def9b8f 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -123,7 +123,7 @@ static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN;
  */
 static u16 /*TODO: Is this really hardware dependent ?*/
 ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates,
-    u32 frame_length, u16 rate_index, bool short_preamble)
+		u32 frame_length, u16 rate_index, bool short_preamble)
 {
 	const struct ath5k_rate *rate;
 	u32 value;
@@ -403,8 +403,8 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc,
 	hal->ah_phy = AR5K_PHY(0);
 
 	/* Set MAC to bcast: ff:ff:ff:ff:ff:ff, this is using 'mac' as a
- 	 * temporary variable for setting our BSSID. Right bellow we update
- 	 * it with ath5k_hw_get_lladdr() */
+	 * temporary variable for setting our BSSID. Right bellow we update
+	 * it with ath5k_hw_get_lladdr() */
 	memset(mac, 0xff, ETH_ALEN);
 	ath5k_hw_set_associd(hal, mac, 0);
 
@@ -1096,7 +1096,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 	if (hal->ah_version != AR5K_AR5210) {
 		ath5k_hw_reg_write(hal, 0xffffffff, AR5K_PISR);
 		/* XXX: AR5K_RSSI_THR has masks and shifts defined for it, so
- 		 * direct write using ath5k_hw_reg_write seems wrong. Test with:
+		 * direct write using ath5k_hw_reg_write seems wrong. Test with:
 		 * AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR,
 		 *   AR5K_RSSI_THR_BMISS, AR5K_TUNE_RSSI_THRES);
 		 * with different variables and check results compared
@@ -1153,8 +1153,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 	}
 
 	/*
- 	 * Enable noise floor calibration and wait until completion
- 	 */
+	 * Enable noise floor calibration and wait until completion
+	 */
 	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL,
 				AR5K_PHY_AGCCTL_NF);
 
@@ -1668,7 +1668,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase)
 
 	status = true;
 
- done:
+done:
 	/*
 	 * Restore interrupt mask
 	 */
@@ -2651,8 +2651,7 @@ ath5k_hw_stop_pcu_recv(struct ath_hw *hal)
  * Set multicast filter
  */
 void
-ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0,
-    u32 filter1)
+ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, u32 filter1)
 {
 	AR5K_TRACE;
 	/* Set the multicat filter */
@@ -2849,7 +2848,7 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *
 {
 	u32 cfp_period, next_cfp, dtim, interval, next_beacon;
 
- 	/*
+	/*
 	 * TODO: should be changed through *state
 	 * review struct ath5k_beacon_state struct
 	 *
@@ -3204,7 +3203,7 @@ int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac)
 	AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
 
 	/* MAC may be NULL if it's a broadcast key. In this case no need to
- 	 * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */
+	 * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */
 	if (unlikely(mac == NULL)) {
 		low_id = 0xffffffff;
 		high_id = 0xffff | AR5K_KEYTABLE_VALID;
@@ -3820,8 +3819,8 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal,
  */
 static bool
 ath5k_hw_setup_xr_tx_desc(struct ath_hw *hal, struct ath_desc *desc,
-    unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
-    unsigned int tx_rate3, u_int tx_tries3)
+	unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
+	unsigned int tx_rate3, u_int tx_tries3)
 {
 	struct ath5k_hw_4w_tx_desc *tx_desc;
 
@@ -4716,8 +4715,8 @@ static int ath5k_hw_rf5110_calibrate(struct ath_hw *hal,
 	}
 
 	/*
- 	 * Enable noise floor calibration and wait until completion
- 	 */
+	 * Enable noise floor calibration and wait until completion
+	 */
 	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF);
 
 	ret = ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
@@ -5671,8 +5670,7 @@ ath5k_hw_query_pspoll_support(struct ath_hw *hal)
 }
 
 bool
-ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid,
-    u16 assoc_id)
+ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id)
 {
 	AR5K_TRACE;
 	if (hal->ah_version == AR5K_AR5210) {

commit 1ee6c2c27fab905aa282016b1c0451d90eb4d15d
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Tue Aug 7 08:12:34 2007 +0200

    remove trailing whitespace

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 85f5a9f..ba76103 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -402,15 +402,15 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc,
 
 	hal->ah_phy = AR5K_PHY(0);
 
-	/* Set MAC to bcast: ff:ff:ff:ff:ff:ff, this is using 'mac' as a 
- 	 * temporary variable for setting our BSSID. Right bellow we update 
+	/* Set MAC to bcast: ff:ff:ff:ff:ff:ff, this is using 'mac' as a
+ 	 * temporary variable for setting our BSSID. Right bellow we update
  	 * it with ath5k_hw_get_lladdr() */
 	memset(mac, 0xff, ETH_ALEN);
 	ath5k_hw_set_associd(hal, mac, 0);
 
 	ath5k_hw_get_lladdr(hal, mac);
 	ath5k_hw_set_opmode(hal);
-		
+
 #ifdef AR5K_DEBUG
 	ath5k_hw_dump_state(hal);
 #endif
@@ -487,7 +487,7 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial)
 		/*
 		 * Get channel mode flags
 		 */
- 
+
 		if (hal->ah_radio >= AR5K_RF5112) {
 			mode = AR5K_PHY_MODE_RAD_RF5112;
 			clock = AR5K_PHY_PLL_RF5112;
@@ -879,7 +879,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 		ath5k_hw_ini_registers(hal, ARRAY_SIZE(ar5210_ini),
 				ar5210_ini, change_channel);
 	}
-	
+
 	/*
 	 * 5211/5212 Specific
 	 */
@@ -921,7 +921,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 						    (AR5K_SET_SHORT_PREAMBLE << 2));
 					}
 				}
-	
+
 			} else {
 			/*For 802.11a/g Turbo/XR mode (AR5K_MODE_XR here is O.K. for both a/g - OFDM)*/
 
@@ -1095,7 +1095,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 	/*PISR/SISR Not available on 5210*/
 	if (hal->ah_version != AR5K_AR5210) {
 		ath5k_hw_reg_write(hal, 0xffffffff, AR5K_PISR);
-		/* XXX: AR5K_RSSI_THR has masks and shifts defined for it, so 
+		/* XXX: AR5K_RSSI_THR has masks and shifts defined for it, so
  		 * direct write using ath5k_hw_reg_write seems wrong. Test with:
 		 * AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR,
 		 *   AR5K_RSSI_THR_BMISS, AR5K_TUNE_RSSI_THRES);
@@ -1173,7 +1173,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 		if (AR5K_PHY_NF_RVAL(noise_floor) &
 		AR5K_PHY_NF_ACTIVE)
 			noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
-	
+
 		if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
 			break;
 	}
@@ -1183,7 +1183,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 			channel->freq);
 		return -EIO;
 	}
-	
+
 	hal->ah_calibration = false;
 
 	if (!(channel->val & CHANNEL_B)) {
@@ -1243,7 +1243,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 			AR5K_PHY_SPENDING);
 	}
 
-	/* 
+	/*
 	 * Disable beacons and reset the register
 	 */
 	AR5K_REG_DISABLE_BITS(hal, AR5K_BEACON, AR5K_BEACON_ENABLE |
@@ -1465,7 +1465,7 @@ int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue)
 				break;
 			case AR5K_TX_QUEUE_BEACON:
 				tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
-				ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | 
+				ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V |
 					AR5K_BCR_BDMAE, AR5K_BSR);
 				break;
 			case AR5K_TX_QUEUE_CAB:
@@ -1554,7 +1554,7 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue)
 /*
  * Get the address of the TX Descriptor for a specific queue
  * (see also QCU/DCU functions)
- */ 
+ */
 u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue)
 {
 	u16 tx_reg;
@@ -1614,7 +1614,7 @@ int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr)
 		}
 	} else {
 		/*
-		 * Set the transmit queue descriptor pointer for 
+		 * Set the transmit queue descriptor pointer for
 		 * the selected queue on QCU for 5211+
 		 * (this won't work if the queue is still active)
 		 */
@@ -1740,8 +1740,8 @@ int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask)
 			*interrupt_mask |= AR5K_INT_BNR;
 	}
 
-	/* 
-	 * XXX: BMISS interrupts may occur after association. 
+	/*
+	 * XXX: BMISS interrupts may occur after association.
 	 * I found this on 5210 code but it needs testing
 	 */
 #if 0
@@ -2427,7 +2427,7 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal)
 		if (AR5K_EEPROM_HDR_11A(ee_header)) {
 			hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */
 			hal->ah_capabilities.cap_range.range_5ghz_max = 6100;
-	
+
 			/* Set supported modes */
 			set_bit(MODE_IEEE80211A, hal->ah_capabilities.cap_mode);
 			set_bit(MODE_ATHEROS_TURBO,
@@ -2436,12 +2436,12 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal)
 				set_bit(MODE_ATHEROS_TURBOG,
 						hal->ah_capabilities.cap_mode);
 		}
-	
+
 		/* Enable  802.11b if a 2GHz capable radio (2111/5112) is connected */
 		if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) {
 			hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
 			hal->ah_capabilities.cap_range.range_2ghz_max = 2732;
-	
+
 			if (AR5K_EEPROM_HDR_11B(ee_header))
 				set_bit(MODE_IEEE80211B,
 						hal->ah_capabilities.cap_mode);
@@ -2610,10 +2610,10 @@ ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask)
 		low_id = AR5K_LOW_ID(mask);
 		high_id = AR5K_HIGH_ID(mask);
 
-		ath5k_hw_reg_write(hal, low_id, AR5K_BSS_IDM0); 
-		ath5k_hw_reg_write(hal, high_id, AR5K_BSS_IDM1); 
+		ath5k_hw_reg_write(hal, low_id, AR5K_BSS_IDM0);
+		ath5k_hw_reg_write(hal, high_id, AR5K_BSS_IDM1);
 
-		return true; 
+		return true;
 	}
 
 	return false;
@@ -2849,7 +2849,7 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *
 {
 	u32 cfp_period, next_cfp, dtim, interval, next_beacon;
 
- 	/* 
+ 	/*
 	 * TODO: should be changed through *state
 	 * review struct ath5k_beacon_state struct
 	 *
@@ -2873,8 +2873,8 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *
 	 * PCF support?
 	 */
 	if (state->bs_cfp_period > 0) {
-		/* 
-		 * Enable PCF mode and set the CFP 
+		/*
+		 * Enable PCF mode and set the CFP
 		 * (Contention Free Period) and timer registers
 		 */
 		cfp_period = state->bs_cfp_period * state->bs_dtim_period *
@@ -2944,7 +2944,7 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *
 
 		if (interval > dtim)
 			return;
-	
+
 		next_beacon = interval == dtim ? state->bs_next_dtim :
 			state->bs_next_beacon;
 
@@ -3203,7 +3203,7 @@ int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac)
 	 /* Invalid entry (key table overflow) */
 	AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
 
-	/* MAC may be NULL if it's a broadcast key. In this case no need to 
+	/* MAC may be NULL if it's a broadcast key. In this case no need to
  	 * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */
 	if (unlikely(mac == NULL)) {
 		low_id = 0xffffffff;
@@ -3255,7 +3255,7 @@ int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type,
 		switch (queue_type) {
 			case AR5K_TX_QUEUE_DATA:
 				for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
-					hal->ah_txq[queue].tqi_type != 
+					hal->ah_txq[queue].tqi_type !=
 					AR5K_TX_QUEUE_INACTIVE; queue++) {
 
 					if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
@@ -3279,7 +3279,7 @@ int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type,
 				break;
 			default:
 				return -EINVAL;
-		}	
+		}
 	}
 
 	/*
@@ -3313,13 +3313,13 @@ int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue,
 	AR5K_TRACE;
 	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
 
-	if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) 
+	if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
 		return -EIO;
 
 	memcpy(&hal->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info));
 
 	/*XXX: Is this supported on 5210 ?*/
-	if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && 
+	if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA &&
 			((queue_info->tqi_subtype == AR5K_WME_AC_VI) ||
 			(queue_info->tqi_subtype == AR5K_WME_AC_VO))) ||
 			queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD)
@@ -3362,7 +3362,7 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 	u32 cw_min, cw_max, retry_lg, retry_sh;
 	struct ath5k_txq_info *tq = &hal->ah_txq[queue];
 	int i;
-	struct ath5k_ar5210_ini_mode ar5210_mode[] = 
+	struct ath5k_ar5210_ini_mode ar5210_mode[] =
 			AR5K_AR5210_INI_MODE(hal, hal->ah_aifs + tq->tqi_aifs);
 
 	AR5K_TRACE;
@@ -3533,7 +3533,7 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 
 				ath5k_hw_reg_write(hal,
 					((AR5K_TUNE_BEACON_INTERVAL -
-					(AR5K_TUNE_SW_BEACON_RESP - 
+					(AR5K_TUNE_SW_BEACON_RESP -
 					AR5K_TUNE_DMA_BEACON_RESP) -
 					AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
 					AR5K_QCU_RDYTIMECFG_ENABLE,
@@ -3572,7 +3572,7 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 			AR5K_SIMR1_QCU_TXERR), AR5K_SIMR1);
 		ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts,
 			AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2);
-	}	
+	}
 
 	return 0;
 }
@@ -4051,10 +4051,10 @@ int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc,
 	rx_desc = (struct ath5k_rx_desc*)&desc->ds_ctl0;
 
 	/*
-	 *Clear ds_hw 
+	 *Clear ds_hw
 	 * If we don't clean the status descriptor,
-	 * while scanning we get too many results, 
-	 * most of them virtual, after some secs 
+	 * while scanning we get too many results,
+	 * most of them virtual, after some secs
 	 * of scanning system hangs. M.F.
 	*/
 	memset(desc->ds_hw, 0, sizeof(desc->ds_hw));
@@ -4382,7 +4382,7 @@ bool ath5k_channel_ok(struct ath_hw *hal, u16 freq, unsigned int flags)
 		if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) &&
 		    (freq <= hal->ah_capabilities.cap_range.range_2ghz_max))
 			return true;
-	} else if (flags & CHANNEL_5GHZ) 
+	} else if (flags & CHANNEL_5GHZ)
 		if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) &&
 		    (freq <= hal->ah_capabilities.cap_range.range_5ghz_max))
 			return true;
@@ -4466,7 +4466,7 @@ static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
 {
 	int channel;
 
-	/* Cast this value to catch negative channel numbers (>= -19) */ 
+	/* Cast this value to catch negative channel numbers (>= -19) */
 	channel = (int)ieee;
 
 	/*
@@ -4735,7 +4735,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath_hw *hal,
 
 		if (AR5K_PHY_NF_RVAL(noise_floor) & AR5K_PHY_NF_ACTIVE)
 			noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
-	
+
 		if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
 			break;
 	}
@@ -5261,7 +5261,7 @@ static int ath5k_hw_rf5112_rfregs(struct ath_hw *hal,
 }
 
 /*
- * Initialize 5211 RF 
+ * Initialize 5211 RF
  * TODO: is this needed ? i mean 5211 has a 5111 RF
  * doesn't ar5k_rfregs work ?
  */
@@ -5459,7 +5459,7 @@ ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel,
 	/* Initialize TX power table */
 	ath5k_txpower_table(hal, channel, txpower);
 
-	/* 
+	/*
 	 * Write TX power values
 	 */
 	for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
@@ -5621,7 +5621,7 @@ int ath5k_hw_get_capability(struct ath_hw *hal,
 	AR5K_TRACE;
 
 	switch (cap_type) {
-	case AR5K_CAP_NUM_TXQUEUES: 
+	case AR5K_CAP_NUM_TXQUEUES:
 		if (result) {
 			if (hal->ah_version == AR5K_AR5210)
 				*result = AR5K_NUM_TX_QUEUES_NOQCU;
@@ -5650,15 +5650,14 @@ int ath5k_hw_get_capability(struct ath_hw *hal,
 			goto yes;
 		else
 			goto no;
-	default: 
+	default:
 		goto no;
 	}
 
- no:
+no:
 	return -EINVAL;
- yes:
+yes:
 	return 0;
-	
 }
 
 bool

commit 755587b3a3dd0294cb1b6818adcf2cfa92ddb8b9
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Sat Aug 4 22:11:11 2007 +0200

    add me to copyrights

diff --git a/ath5k_hw.c b/ath5k_hw.c
index fee1d0b..85f5a9f 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -1,6 +1,7 @@
  /*
  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
  * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
+ * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
  *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above

commit f61a61790b5500179ca7b70b73dd8b123a7ef6de
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Sat Aug 4 08:31:08 2007 +0200

    add delay.h to includes

diff --git a/ath5k_hw.c b/ath5k_hw.c
index fe37c93..fee1d0b 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -21,6 +21,7 @@
  */
 
 #include <linux/pci.h>
+#include <linux/delay.h>
 
 #include "ath5k.h"
 #include "ath5k_reg.h"

commit e6f01ced4b546b08001ab049ac09dd600a0126c6
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Sat Aug 4 08:16:22 2007 +0200

    revert 307af1838f7d3ac4127742ac8c988ce347e05140

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 541228e..fe37c93 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -22,7 +22,7 @@
 
 #include <linux/pci.h>
 
-#include "ath5k_hw.h"
+#include "ath5k.h"
 #include "ath5k_reg.h"
 
 /*Rate tables*/

commit 38fe84ecf5d4f69eed707ac123c701239596285c
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Fri Aug 3 23:02:24 2007 +0200

    ieee80211_regdomain -> ath5k_regdom

diff --git a/ath5k_hw.c b/ath5k_hw.c
index eb02bdd..541228e 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -2343,22 +2343,22 @@ static int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac)
  * Read/Write regulatory domain
  */
 static bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write,
-	enum ieee80211_regdomain *regdomain)
+	enum ath5k_regdom *regdomain)
 {
 	u16 ee_regdomain;
 
 	/* Read current value */
 	if (write != true) {
 		ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain;
-		*regdomain = ath5k_regdomain_to_ieee(ee_regdomain);
+		*regdomain = ath5k_regdom_to_ieee(ee_regdomain);
 		return true;
 	}
 
-	ee_regdomain = ath5k_regdomain_from_ieee(*regdomain);
+	ee_regdomain = ath5k_regdom_from_ieee(*regdomain);
 
 	/* Try to write a new value */
 	if (hal->ah_capabilities.cap_eeprom.ee_protect &
-	    AR5K_EEPROM_PROTECT_WR_128_191)
+			AR5K_EEPROM_PROTECT_WR_128_191)
 		return false;
 	if (ath5k_hw_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, ee_regdomain)!=0)
 		return false;
@@ -2373,9 +2373,9 @@ static bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write,
  */
 int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain)
 {
-	enum ieee80211_regdomain ieee_regdomain;
+	enum ath5k_regdom ieee_regdomain;
 
-	ieee_regdomain = ath5k_regdomain_to_ieee(regdomain);
+	ieee_regdomain = ath5k_regdom_to_ieee(regdomain);
 
 	if (ath5k_eeprom_regulation_domain(hal, true, &ieee_regdomain) == true)
 		return 0;
@@ -4391,7 +4391,7 @@ bool ath5k_channel_ok(struct ath_hw *hal, u16 freq, unsigned int flags)
 u16 ath5k_get_regdomain(struct ath_hw *hal)
 {
 	u16 regdomain;
-	enum ieee80211_regdomain ieee_regdomain;
+	enum ath5k_regdom ieee_regdomain;
 #ifdef COUNTRYCODE
 	u16 code;
 #endif
@@ -4408,7 +4408,7 @@ u16 ath5k_get_regdomain(struct ath_hw *hal)
 	ieee_regdomain = ieee80211_countrycode2regdomain(code);
 #endif
 
-	regdomain = ath5k_regdomain_from_ieee(ieee_regdomain);
+	regdomain = ath5k_regdom_from_ieee(ieee_regdomain);
 	hal->ah_capabilities.cap_regdomain.reg_current = regdomain;
 
 	return regdomain;

commit 307af1838f7d3ac4127742ac8c988ce347e05140
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Fri Aug 3 22:55:11 2007 +0200

    remove ath5k.h and move the stuff to the ath5k_hw.h mostly

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 501d85c..eb02bdd 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -22,7 +22,7 @@
 
 #include <linux/pci.h>
 
-#include "ath5k.h"
+#include "ath5k_hw.h"
 #include "ath5k_reg.h"
 
 /*Rate tables*/

commit b04cebfdf1788804d0578f818ed102de04a5614c
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Tue Jul 24 13:02:23 2007 +0200

    IBSS mode

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 0dae6a4..501d85c 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -1200,9 +1200,10 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 		if (hal->ah_version != AR5K_AR5210)
 			AR5K_REG_WRITE_Q(hal, AR5K_QUEUE_QCUMASK(i), i);
 
-		if (ath5k_hw_reset_tx_queue(hal, i) == false) {
+		ret = ath5k_hw_reset_tx_queue(hal, i);
+		if (ret) {
 			AR5K_PRINTF("failed to reset TX queue #%d\n", i);
-			return -EINVAL;
+			return ret;
 		}
 	}
 
@@ -2560,8 +2561,7 @@ ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac)
  * Set BSSID
  */
 void
-ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid,
-    u16 assoc_id)
+ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id)
 {
 	u32 low_id, high_id;
 	u16 tim_offset = 0;
@@ -2797,9 +2797,7 @@ void ath5k_hw_reset_tsf(struct ath_hw *hal)
 /*
  * Initialize beacon timers
  */
-void
-ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon,
-		u32 interval)
+void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32 interval)
 {
 	u32 timer1, timer2, timer3;
 
@@ -3331,12 +3329,12 @@ int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue,
 /*
  * Get properties for a specific transmit queue
  */
-bool
-ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info)
+int ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue,
+		struct ath5k_txq_info *queue_info)
 {
 	AR5K_TRACE;
 	memcpy(queue_info, &hal->ah_txq[queue], sizeof(struct ath5k_txq_info));
-	return true;
+	return 0;
 }
 
 /*
@@ -3345,10 +3343,8 @@ ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info
 void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue)
 {
 	AR5K_TRACE;
-	if (queue >= hal->ah_capabilities.cap_queues.q_tx_num) {
-		WARN_ON(1);
+	if (WARN_ON(queue >= hal->ah_capabilities.cap_queues.q_tx_num))
 		return;
-	}
 
 	/* This queue will be skipped in further operations */
 	hal->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
@@ -3359,8 +3355,7 @@ void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue)
 /*
  * Set DFS params for a transmit queue
  */
-bool
-ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
+int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 {
 	u32 cw_min, cw_max, retry_lg, retry_sh;
 	struct ath5k_txq_info *tq = &hal->ah_txq[queue];
@@ -3374,12 +3369,12 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 	tq = &hal->ah_txq[queue];
 
 	if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
-		return true;
+		return 0;
 
 	if (hal->ah_version == AR5K_AR5210) {
 		/* Only handle data queues, others will be ignored */
 		if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
-			return true;
+			return -EINVAL;
 
 		/*
 		 * Write initial mode register settings
@@ -3577,7 +3572,7 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 			AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2);
 	}	
 
-	return true;
+	return 0;
 }
 
 /*

commit bfaae2441d32f14130888743ab46a3dc88938b62
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Sat Jul 21 11:51:01 2007 +0200

    ath5k_hw_set_opmode whitespace cleanup

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 096f267..0dae6a4 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -2480,27 +2480,27 @@ ath5k_hw_set_opmode(struct ath_hw *hal)
 
 	switch (hal->ah_op_mode) {
 	case IEEE80211_IF_TYPE_IBSS:
-		pcu_reg |= AR5K_STA_ID1_ADHOC |
-			AR5K_STA_ID1_DESC_ANTENNA |
-			(hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0);
-
+		pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_DESC_ANTENNA |
+			(hal->ah_version == AR5K_AR5210 ?
+				AR5K_STA_ID1_NO_PSPOLL : 0);
 		beacon_reg |= AR5K_BCR_ADHOC;
 		break;
 
 	case IEEE80211_IF_TYPE_AP:
-		pcu_reg |= AR5K_STA_ID1_AP |
-			AR5K_STA_ID1_RTS_DEF_ANTENNA |
-			(hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0);
-
+		pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_RTS_DEF_ANTENNA |
+			(hal->ah_version == AR5K_AR5210 ?
+				AR5K_STA_ID1_NO_PSPOLL : 0);
 		beacon_reg |= AR5K_BCR_AP;
 		break;
 
 	case IEEE80211_IF_TYPE_STA:
 		pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
-			(hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_PWR_SV :0);
+			(hal->ah_version == AR5K_AR5210 ?
+				AR5K_STA_ID1_PWR_SV : 0);
 	case IEEE80211_IF_TYPE_MNTR:
 		pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
-			(hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0);
+			(hal->ah_version == AR5K_AR5210 ?
+				AR5K_STA_ID1_NO_PSPOLL : 0);
 		break;
 
 	default:

commit 316fc03fe784c48140839968fd2c6fc7bb8b714a
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Thu Jul 19 08:25:15 2007 +0200

    promisc

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 4cfafc8..096f267 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -2723,8 +2723,7 @@ ath5k_hw_get_rx_filter(struct ath_hw *ah)
 /*
  * Set rx filter
  */
-void
-ath5k_hw_set_rx_filter(struct ath_hw *ah, u32 filter)
+void ath5k_hw_set_rx_filter(struct ath_hw *ah, u32 filter)
 {
 	u32 data = 0;
 

commit a3eda4e3c3e5dd2f79111f8de0d9d09fc900e257
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Thu Jul 19 07:26:12 2007 +0200

    RX_FILTER cleanup (remove double defs)

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 80a6ca8..4cfafc8 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -2700,19 +2700,19 @@ ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index)
  * Get current rx filter
  */
 u32
-ath5k_hw_get_rx_filter(struct ath_hw *hal)
+ath5k_hw_get_rx_filter(struct ath_hw *ah)
 {
 	u32 data, filter = 0;
 
 	AR5K_TRACE;
-	filter = ath5k_hw_reg_read(hal, AR5K_RX_FILTER);
+	filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
 
 	/*Radar detection for 5212*/
-	if (hal->ah_version == AR5K_AR5212) {
-		data = ath5k_hw_reg_read(hal, AR5K_PHY_ERR_FIL);
+	if (ah->ah_version == AR5K_AR5212) {
+		data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
 
 		if (data & AR5K_PHY_ERR_FIL_RADAR)
-			filter |= AR5K_RX_FILTER_PHYRADAR;
+			filter |= AR5K_RX_FILTER_RADARERR;
 		if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
 			filter |= AR5K_RX_FILTER_PHYERR;
 	}
@@ -2724,15 +2724,15 @@ ath5k_hw_get_rx_filter(struct ath_hw *hal)
  * Set rx filter
  */
 void
-ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter)
+ath5k_hw_set_rx_filter(struct ath_hw *ah, u32 filter)
 {
 	u32 data = 0;
 
 	AR5K_TRACE;
 
 	/* Set PHY error filter register on 5212*/
-	if (hal->ah_version == AR5K_AR5212) {
-		if (filter & AR5K_RX_FILTER_PHYRADAR)
+	if (ah->ah_version == AR5K_AR5212) {
+		if (filter & AR5K_RX_FILTER_RADARERR)
 			data |= AR5K_PHY_ERR_FIL_RADAR;
 		if (filter & AR5K_RX_FILTER_PHYERR)
 			data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
@@ -2741,24 +2741,24 @@ ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter)
 	/*
 	 * The AR5210 uses promiscous mode to detect radar activity
 	 */
-	if ((hal->ah_version == AR5K_AR5210) && 
-			(filter & AR5K_RX_FILTER_PHYRADAR)) {
-		filter &= ~AR5K_RX_FILTER_PHYRADAR;
+	if (ah->ah_version == AR5K_AR5210 &&
+			(filter & AR5K_RX_FILTER_RADARERR)) {
+		filter &= ~AR5K_RX_FILTER_RADARERR;
 		filter |= AR5K_RX_FILTER_PROM;
 	}
 
 	/*Zero length DMA*/
 	if (data)
-		AR5K_REG_ENABLE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
+		AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
 	else
-		AR5K_REG_DISABLE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
+		AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
 
 	/*Write RX Filter register*/
-	ath5k_hw_reg_write(hal, filter & 0xff, AR5K_RX_FILTER);
+	ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
 
 	/*Write PHY error filter register on 5212*/
-	if (hal->ah_version == AR5K_AR5212)
-		ath5k_hw_reg_write(hal, data, AR5K_PHY_ERR_FIL);
+	if (ah->ah_version == AR5K_AR5212)
+		ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
 
 }
 

commit 9f55076a5d63e32aba592df0c1323b0d48032e27
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Wed Jul 18 08:23:23 2007 +0200

    ath5k_hw whitespace cleanup

diff --git a/ath5k_hw.c b/ath5k_hw.c
index f74fddc..80a6ca8 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -600,10 +600,9 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial)
 /*
  * Get the PHY Chip revision
  */
-static u16
-ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan)
+static u16 ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan)
 {
-	int i;
+	unsigned int i;
 	u32 srev;
 	u16 ret;
 
@@ -633,12 +632,10 @@ ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan)
 
 	if (hal->ah_version == AR5K_AR5210) {
 		srev = ath5k_hw_reg_read(hal, AR5K_PHY(256) >> 28) & 0xf;
-
-		ret = (u16) ath5k_hw_bitswap(srev, 4) + 1;
+		ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
 	} else {
 		srev = (ath5k_hw_reg_read(hal, AR5K_PHY(0x100)) >> 24) & 0xff;
-
-		ret = (u16) ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8);
+		ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8);
 	}
 
 	/* Reset to the 5GHz mode */
@@ -651,15 +648,15 @@ ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan)
  * Get the rate table for a specific operation mode
  * TODO:Limit this per chipset
  */
-const struct ath5k_rate_table *
-ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode)
+const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal,
+		unsigned int mode)
 {
 	AR5K_TRACE;
 
-	/* Get rate tables */
 	if (!test_bit(mode, hal->ah_capabilities.cap_mode))
 		return NULL;
 
+	/* Get rate tables */
 	switch (mode) {
 	case MODE_IEEE80211A:
 		return &ath5k_rt_11a;
@@ -671,8 +668,6 @@ ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode)
 		return &ath5k_rt_11g;
 	case MODE_ATHEROS_TURBOG:
 		return &ath5k_rt_xr;
-	default:
-		return NULL;
 	}
 
 	return NULL;
@@ -1018,13 +1013,12 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 
 		/* Set antenna mode */
 		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x44),
-		    hal->ah_antenna[ee_mode][0], 0xfffffc06);
-
-			if (freq == AR5K_INI_RFGAIN_2GHZ)
-				ant[0] = ant[1] = AR5K_ANT_FIXED_B;
-			else
-				ant[0] = ant[1] = AR5K_ANT_FIXED_A;
+			hal->ah_antenna[ee_mode][0], 0xfffffc06);
 
+		if (freq == AR5K_INI_RFGAIN_2GHZ)
+			ant[0] = ant[1] = AR5K_ANT_FIXED_B;
+		else
+			ant[0] = ant[1] = AR5K_ANT_FIXED_A;
 
 		ath5k_hw_reg_write(hal, hal->ah_antenna[ee_mode][ant[0]],
 			AR5K_PHY_ANT_SWITCH_TABLE_0);
@@ -1067,8 +1061,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 
 		if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
 			AR5K_REG_WRITE_BITS(hal, AR5K_PHY_GAIN_2GHZ,
-			    AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
-			    ee->ee_margin_tx_rx[ee_mode]);
+				AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
+				ee->ee_margin_tx_rx[ee_mode]);
 		}
 
 	} else {
@@ -1152,8 +1146,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 
 	if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
 			AR5K_PHY_AGCCTL_CAL, 0, false)) {
-		AR5K_PRINTF("calibration timeout (%uMHz)\n",
-		    channel->freq);
+		AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq);
 		return -EAGAIN;
 	}
 
@@ -1194,9 +1187,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 	if (!(channel->val & CHANNEL_B)) {
 		hal->ah_calibration = true;
 		AR5K_REG_WRITE_BITS(hal, AR5K_PHY_IQ,
-		    AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
+				AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
 		AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ,
-		    AR5K_PHY_IQ_RUN);
+				AR5K_PHY_IQ_RUN);
 	}
 
 	/*
@@ -1250,8 +1243,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 	/* 
 	 * Disable beacons and reset the register
 	 */
-	AR5K_REG_DISABLE_BITS(hal, AR5K_BEACON,
-	    AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF);
+	AR5K_REG_DISABLE_BITS(hal, AR5K_BEACON, AR5K_BEACON_ENABLE |
+			AR5K_BEACON_RESET_TSF);
 
 	return 0;
 }
@@ -1281,11 +1274,8 @@ static int ath5k_hw_nic_reset(struct ath_hw *hal, u32 val)
 		val &= AR5K_RESET_CTL_CHIP;
 		mask &= AR5K_RESET_CTL_CHIP;
 	} else {
-		val &=
-		    AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
-
-		mask &=
-		    AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
+		val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
+		mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
 	}
 
 	ret = ath5k_hw_register_timeout(hal, AR5K_RESET_CTL, mask, val, false);
@@ -1309,8 +1299,8 @@ static int ath5k_hw_nic_reset(struct ath_hw *hal, u32 val)
 int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode,
 		bool set_chip, u16 sleep_duration)
 {
+	unsigned int i;
 	u32 staid;
-	int i;
 
 	AR5K_TRACE;
 	staid = ath5k_hw_reg_read(hal, AR5K_STA_ID1);
@@ -1345,7 +1335,7 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode,
 		for (i = 5000; i > 0; i--) {
 			/* Check if the chip did wake up */
 			if ((ath5k_hw_reg_read(hal, AR5K_PCICFG) &
-			    AR5K_PCICFG_SPWR_DN) == 0)
+					AR5K_PCICFG_SPWR_DN) == 0)
 				break;
 
 			/* Wait a bit and retry */
@@ -1384,8 +1374,6 @@ ath5k_hw_get_power_mode(struct ath_hw *hal)
 }
 
 
-
-
 /***********************\
   DMA Related Functions
 \***********************/
@@ -1507,8 +1495,8 @@ int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue)
 bool
 ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue)
 {
-	int i = 100, pending;
-	u32 tx_queue;
+	unsigned int i = 100;
+	u32 tx_queue, pending;
 
 	AR5K_TRACE;
 	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
@@ -1564,10 +1552,10 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue)
  * Get the address of the TX Descriptor for a specific queue
  * (see also QCU/DCU functions)
  */ 
-u32
-ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue)
+u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue)
 {
 	u16 tx_reg;
+
 	AR5K_TRACE;
 	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
 
@@ -1601,6 +1589,7 @@ ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue)
 int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr)
 {
 	u16 tx_reg;
+
 	AR5K_TRACE;
 	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
 
@@ -1646,6 +1635,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase)
 {
 	u32 trigger_level, imr;
 	bool status = false;
+
 	AR5K_TRACE;
 
 	/*
@@ -1814,7 +1804,7 @@ enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask)
 }
 
 /*
- * Enalbe HW radar detection
+ * Enable HW radar detection
  */
 void
 ath5k_hw_radar_alert(struct ath_hw *hal, bool enable)
@@ -1833,13 +1823,10 @@ ath5k_hw_radar_alert(struct ath_hw *hal, bool enable)
 	 * possible radar activity.
 	 */
 	if (hal->ah_version == AR5K_AR5210) {
-		if (enable == true) {
-			AR5K_REG_ENABLE_BITS(hal, AR5K_IMR,
-					AR5K_IMR_RXPHY);
-		} else {
-			AR5K_REG_DISABLE_BITS(hal, AR5K_IMR,
-					AR5K_IMR_RXPHY);
-		}
+		if (enable == true)
+			AR5K_REG_ENABLE_BITS(hal, AR5K_IMR, AR5K_IMR_RXPHY);
+		else
+			AR5K_REG_DISABLE_BITS(hal, AR5K_IMR, AR5K_IMR_RXPHY);
 	} else {
 		/*Also set AR5K_PHY_RADAR register on 5111/5112*/
 		if (enable == true) {
@@ -1891,8 +1878,8 @@ static int ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data)
 		if (status & AR5K_EEPROM_STAT_RDDONE) {
 			if (status & AR5K_EEPROM_STAT_RDERR)
 				return -EIO;
-			*data = (u16)
-			    (ath5k_hw_reg_read(hal, AR5K_EEPROM_DATA) & 0xffff);
+			*data = (u16)(ath5k_hw_reg_read(hal, AR5K_EEPROM_DATA) &
+					0xffff);
 			return 0;
 		}
 		udelay(15);
@@ -1962,9 +1949,8 @@ static u16 ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode)
 		if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
 			val = (5 * bin) + 4800;
 		else
-			val = bin > 62 ?
-			    (10 * 62) + (5 * (bin - 62)) + 5100 :
-			    (bin * 10) + 5100;
+			val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
+				(bin * 10) + 5100;
 	} else {
 		if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
 			val = bin + 2300;
@@ -2050,8 +2036,7 @@ static int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset,
 	ee->ee_thr_62[mode]		= val & 0xff;
 
 	if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
-		ee->ee_thr_62[mode] =
-		    mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
+		ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
 
 	AR5K_EEPROM_READ(o++, val);
 	ee->ee_tx_end2xpa_disable[mode]	= (val >> 8) & 0xff;
@@ -2103,7 +2088,7 @@ static int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset,
 	}
 
 	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
-	    mode == AR5K_EEPROM_MODE_11A) {
+			mode == AR5K_EEPROM_MODE_11A) {
 		ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
 		ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
 	}
@@ -2124,10 +2109,10 @@ static int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset,
 static int ath5k_eeprom_init(struct ath_hw *hal)
 {
 	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
+	unsigned int mode, i;
+	int ret;
 	u32 offset;
 	u16 val;
-	int ret, i;
-	unsigned int mode;
 
 	/* Initial TX thermal adjustment values */
 	ee->ee_tx_clip = 4;
@@ -2197,8 +2182,7 @@ static int ath5k_eeprom_init(struct ath_hw *hal)
 	 */
 	mode = AR5K_EEPROM_MODE_11A;
 
-	ee->ee_turbo_max_power[mode] =
-	    AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
+	ee->ee_turbo_max_power[mode] = AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
 
 	offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version);
 
@@ -2251,13 +2235,13 @@ static int ath5k_eeprom_init(struct ath_hw *hal)
 	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
 		AR5K_EEPROM_READ(offset++, val);
 		ee->ee_cal_pier[mode][0] =
-		    ath5k_eeprom_bin2freq(hal, val & 0xff, mode);
+			ath5k_eeprom_bin2freq(hal, val & 0xff, mode);
 		ee->ee_cal_pier[mode][1] =
-		    ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
+			ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
 
 		AR5K_EEPROM_READ(offset++, val);
 		ee->ee_cal_pier[mode][2] =
-		    ath5k_eeprom_bin2freq(hal, val & 0xff, mode);
+			ath5k_eeprom_bin2freq(hal, val & 0xff, mode);
 	}
 
 	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
@@ -2286,9 +2270,9 @@ static int ath5k_eeprom_init(struct ath_hw *hal)
 	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
 		AR5K_EEPROM_READ(offset++, val);
 		ee->ee_cal_pier[mode][0] =
-		    ath5k_eeprom_bin2freq(hal, val & 0xff, mode);
+			ath5k_eeprom_bin2freq(hal, val & 0xff, mode);
 		ee->ee_cal_pier[mode][1] =
-		    ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
+			ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
 
 		AR5K_EEPROM_READ(offset++, val);
 		ee->ee_turbo_max_power[mode] = val & 0x7f;
@@ -2296,11 +2280,10 @@ static int ath5k_eeprom_init(struct ath_hw *hal)
 
 		AR5K_EEPROM_READ(offset++, val);
 		ee->ee_cal_pier[mode][2] =
-		    ath5k_eeprom_bin2freq(hal, val & 0xff, mode);
+			ath5k_eeprom_bin2freq(hal, val & 0xff, mode);
 
-		if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
+		if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
 			ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
-		}
 
 		AR5K_EEPROM_READ(offset++, val);
 		ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
@@ -2336,8 +2319,7 @@ static int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac)
 	if (ret)
 		return ret;
 
-	for (offset = 0x1f, octet = 0, total = 0;
-	     offset >= 0x1d; offset--) {
+	for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
 		ret = ath5k_hw_eeprom_read(hal, offset, &data);
 		if (ret)
 			return ret;
@@ -2377,8 +2359,7 @@ static bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write,
 	if (hal->ah_capabilities.cap_eeprom.ee_protect &
 	    AR5K_EEPROM_PROTECT_WR_128_191)
 		return false;
-	if (ath5k_hw_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN,
-	    ee_regdomain) != 0)
+	if (ath5k_hw_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, ee_regdomain)!=0)
 		return false;
 
 	hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain;
@@ -2548,8 +2529,7 @@ ath5k_hw_set_opmode(struct ath_hw *hal)
 /*
  * Get station id
  */
-void
-ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac)
+void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac)
 {
 	AR5K_TRACE;
 	memcpy(mac, hal->ah_sta_id, ETH_ALEN);
@@ -2610,7 +2590,7 @@ ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid,
 	}
 
 	AR5K_REG_WRITE_BITS(hal, AR5K_BEACON, AR5K_BEACON_TIM,
-	    tim_offset ? tim_offset + 4 : 0);
+			tim_offset ? tim_offset + 4 : 0);
 
 	ath5k_hw_enable_pspoll(hal, NULL, 0);
 }
@@ -2625,7 +2605,6 @@ ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask)
 	AR5K_TRACE;
 
 	if (hal->ah_version == AR5K_AR5212) {
-
 		low_id = AR5K_LOW_ID(mask);
 		high_id = AR5K_HIGH_ID(mask);
 
@@ -2633,8 +2612,9 @@ ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask)
 		ath5k_hw_reg_write(hal, high_id, AR5K_BSS_IDM1); 
 
 		return true; 
-	} else
-		return false;
+	}
+
+	return false;
 }
 
 /*
@@ -2687,13 +2667,12 @@ ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index)
 
 	AR5K_TRACE;
 	if (index >= 64)
-	    return false;
+		return false;
 	else if (index >= 32)
-	    AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER1,
-		(1 << (index - 32)));
+		AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER1,
+				(1 << (index - 32)));
 	else
-	    AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER0,
-		(1 << index));
+		AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER0, (1 << index));
 
 	return true;
 }
@@ -2707,13 +2686,12 @@ ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index)
 
 	AR5K_TRACE;
 	if (index >= 64)
-	    return false;
+		return false;
 	else if (index >= 32)
-	    AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER1,
-		(1 << (index - 32)));
+		AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER1,
+				(1 << (index - 32)));
 	else
-	    AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER0,
-		(1 << index));
+		AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER0, (1 << index));
 
 	return true;
 }
@@ -2735,8 +2713,7 @@ ath5k_hw_get_rx_filter(struct ath_hw *hal)
 
 		if (data & AR5K_PHY_ERR_FIL_RADAR)
 			filter |= AR5K_RX_FILTER_PHYRADAR;
-		if (data & (AR5K_PHY_ERR_FIL_OFDM |
-			AR5K_PHY_ERR_FIL_CCK))
+		if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
 			filter |= AR5K_RX_FILTER_PHYERR;
 	}
 
@@ -2758,8 +2735,7 @@ ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter)
 		if (filter & AR5K_RX_FILTER_PHYRADAR)
 			data |= AR5K_PHY_ERR_FIL_RADAR;
 		if (filter & AR5K_RX_FILTER_PHYERR)
-			data |= AR5K_PHY_ERR_FIL_OFDM |
-				AR5K_PHY_ERR_FIL_CCK;
+			data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
 	}
 
 	/*
@@ -2773,11 +2749,9 @@ ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter)
 
 	/*Zero length DMA*/
 	if (data)
-		AR5K_REG_ENABLE_BITS(hal, AR5K_RXCFG,
-				AR5K_RXCFG_ZLFDMA);
+		AR5K_REG_ENABLE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
 	else
-		AR5K_REG_DISABLE_BITS(hal, AR5K_RXCFG,
-				AR5K_RXCFG_ZLFDMA);
+		AR5K_REG_DISABLE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
 
 	/*Write RX Filter register*/
 	ath5k_hw_reg_write(hal, filter & 0xff, AR5K_RX_FILTER);
@@ -2826,7 +2800,7 @@ void ath5k_hw_reset_tsf(struct ath_hw *hal)
  */
 void
 ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon,
-    u32 interval)
+		u32 interval)
 {
 	u32 timer1, timer2, timer3;
 
@@ -2852,8 +2826,7 @@ ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon,
 		    0x00000003;
 	}
 
-	timer3 = next_beacon +
-	    (hal->ah_atim_window ? hal->ah_atim_window : 1);
+	timer3 = next_beacon + (hal->ah_atim_window ? hal->ah_atim_window : 1);
 
 	/*
 	 * Set the beacon register and enable all timers.
@@ -2906,9 +2879,9 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *
 		 * (Contention Free Period) and timer registers
 		 */
 		cfp_period = state->bs_cfp_period * state->bs_dtim_period *
-		    state->bs_interval;
+			state->bs_interval;
 		next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
-		    state->bs_interval;
+			state->bs_interval;
 
 		AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1,
 				AR5K_STA_ID1_DEFAULT_ANTENNA |
@@ -2945,8 +2918,8 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *
 	 * setting value to a largest value and seeing which values register.
 	 */
 
-	AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR,
-	    AR5K_RSSI_THR_BMISS, state->bs_bmiss_threshold);
+	AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS,
+			state->bs_bmiss_threshold);
 
 	/*
 	 * Set sleep control register
@@ -2960,21 +2933,21 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *
 	 * Set enhanced sleep registers on 5212
 	 */
 	if (hal->ah_version == AR5K_AR5212) {
-		if ((state->bs_sleep_duration > state->bs_interval) &&
-		(roundup(state->bs_sleep_duration, interval) ==
-		state->bs_sleep_duration))
+		if (state->bs_sleep_duration > state->bs_interval &&
+				roundup(state->bs_sleep_duration, interval) ==
+				state->bs_sleep_duration)
 			interval = state->bs_sleep_duration;
 
-		if (state->bs_sleep_duration > dtim &&
-		(dtim == 0 || roundup(state->bs_sleep_duration, dtim) ==
-		state->bs_sleep_duration))
+		if (state->bs_sleep_duration > dtim && (dtim == 0 ||
+				roundup(state->bs_sleep_duration, dtim) ==
+				state->bs_sleep_duration))
 			dtim = state->bs_sleep_duration;
 
 		if (interval > dtim)
 			return;
 	
-		next_beacon = interval == dtim ?
-			state->bs_next_dtim: state->bs_next_beacon;
+		next_beacon = interval == dtim ? state->bs_next_dtim :
+			state->bs_next_beacon;
 
 		ath5k_hw_reg_write(hal,
 			AR5K_REG_SM((state->bs_next_dtim - 3) << 3,
@@ -3009,8 +2982,7 @@ ath5k_hw_reset_beacon(struct ath_hw *hal)
 	 * Disable some beacon register values
 	 */
 	AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1,
-				AR5K_STA_ID1_DEFAULT_ANTENNA | 
-				AR5K_STA_ID1_PCF);
+			AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF);
 	ath5k_hw_reg_write(hal, AR5K_BEACON_PERIOD, AR5K_BEACON);
 }
 
@@ -3021,8 +2993,8 @@ ath5k_hw_reset_beacon(struct ath_hw *hal)
 bool
 ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr)
 {
+	unsigned int i;
 	bool ret;
-	int i;
 
 	AR5K_TRACE;
 
@@ -3032,9 +3004,13 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr)
 		 * Wait for beaconn queue to finish by checking
 		 * Control Register and Beacon Status Register.
 		 */
-		for (i = (AR5K_TUNE_BEACON_INTERVAL / 2); i > 0 &&
-		(ath5k_hw_reg_read(hal, AR5K_BSR) & AR5K_BSR_TXQ1F) != 0 &&
-		(ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_CR_TXE1 ) != 0; i--);
+		for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) {
+			if (!(ath5k_hw_reg_read(hal, AR5K_BSR) & AR5K_BSR_TXQ1F)
+					||
+			    !(ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_BSR_TXQ1F))
+				break;
+			udelay(10);
+		}
 
 		/* Timeout... */
 		if (i <= 0) {
@@ -3042,12 +3018,12 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr)
 			 * Re-schedule the beacon queue
 			 */
 			ath5k_hw_reg_write(hal, phys_addr, AR5K_NOQCU_TXDP1);
-			ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, AR5K_BCR);
+			ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
+					AR5K_BCR);
 
 			return false;
 		}
-		ret= true;
-
+		ret = true;
 	} else {
 	/*5211/5212*/
 		ret = ath5k_hw_register_timeout(hal,
@@ -3096,11 +3072,11 @@ ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout)
 {
 	AR5K_TRACE;
 	if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK),
-	    hal->ah_turbo) <= timeout)
+			hal->ah_turbo) <= timeout)
 		return false;
 
 	AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
-	    ath5k_hw_htoclock(timeout, hal->ah_turbo));
+		ath5k_hw_htoclock(timeout, hal->ah_turbo));
 
 	return true;
 }
@@ -3112,8 +3088,9 @@ unsigned int
 ath5k_hw_get_ack_timeout(struct ath_hw *hal)
 {
 	AR5K_TRACE;
-	return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TIME_OUT),
-	    AR5K_TIME_OUT_ACK), hal->ah_turbo));
+
+	return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal,
+			AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), hal->ah_turbo));
 }
 
 /*
@@ -3124,11 +3101,11 @@ ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout)
 {
 	AR5K_TRACE;
 	if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS),
-	    hal->ah_turbo) <= timeout)
+			hal->ah_turbo) <= timeout)
 		return false;
 
 	AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
-	    ath5k_hw_htoclock(timeout, hal->ah_turbo));
+			ath5k_hw_htoclock(timeout, hal->ah_turbo));
 
 	return true;
 }
@@ -3140,8 +3117,8 @@ unsigned int
 ath5k_hw_get_cts_timeout(struct ath_hw *hal)
 {
 	AR5K_TRACE;
-	return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TIME_OUT),
-	    AR5K_TIME_OUT_CTS), hal->ah_turbo));
+	return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal,
+			AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), hal->ah_turbo));
 }
 
 /*
@@ -3298,7 +3275,7 @@ int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type,
 			case AR5K_TX_QUEUE_XR_DATA:
 				if (hal->ah_version != AR5K_AR5212)
 					AR5K_PRINTF("XR data queues only "
-							"supported in 5212!");
+							"supported in 5212!\n");
 				queue = AR5K_TX_QUEUE_ID_XR_DATA;
 				break;
 			default:
@@ -3422,14 +3399,14 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 	cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX;
 	hal->ah_aifs = AR5K_TUNE_AIFS;
 	/*XR is only supported on 5212*/
-	if (IS_CHAN_XR(hal->ah_current_channel)
-			&& (hal->ah_version == AR5K_AR5212)) {
+	if (IS_CHAN_XR(hal->ah_current_channel) &&
+			hal->ah_version == AR5K_AR5212) {
 		cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_XR;
 		cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR;
 		hal->ah_aifs = AR5K_TUNE_AIFS_XR;
 	/*B mode is not supported on 5210*/
-	} else if (IS_CHAN_B(hal->ah_current_channel)
-			&& (hal->ah_version != AR5K_AR5210)) {
+	} else if (IS_CHAN_B(hal->ah_current_channel) &&
+			hal->ah_version != AR5K_AR5210) {
 		cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_11B;
 		cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B;
 		hal->ah_aifs = AR5K_TUNE_AIFS_11B;
@@ -3439,12 +3416,10 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 	while (cw_min < hal->ah_cw_min)
 		cw_min = (cw_min << 1) | 1;
 
-	cw_min = tq->tqi_cw_min < 0 ?
-	    (cw_min >> (-tq->tqi_cw_min)) :
-	    ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
-	cw_max = tq->tqi_cw_max < 0 ?
-	    (cw_max >> (-tq->tqi_cw_max)) :
-	    ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
+	cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) :
+		((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
+	cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) :
+		((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
 
 	/*
 	 * Calculate and set retry limits
@@ -3452,9 +3427,8 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 	if (hal->ah_software_retry == true) {
 		/* XXX Need to test this */
 		retry_lg = hal->ah_limit_tx_retries;
-		retry_sh = retry_lg =
-		    retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
-		    AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
+		retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
+			AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
 	} else {
 		retry_lg = AR5K_INIT_LG_RETRY;
 		retry_sh = AR5K_INIT_SH_RETRY;
@@ -3509,7 +3483,8 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 			AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue),
 				AR5K_QCU_MISC_FRSHED_CBR);
 			if (tq->tqi_cbr_overflow_limit)
-				AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue),
+				AR5K_REG_ENABLE_BITS(hal,
+					AR5K_QUEUE_MISC(queue),
 					AR5K_QCU_MISC_CBR_THRES_ENABLE);
 		}
 
@@ -3547,12 +3522,14 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 		 */
 		switch (tq->tqi_type) {
 			case AR5K_TX_QUEUE_BEACON:
-				AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue),
+				AR5K_REG_ENABLE_BITS(hal,
+					AR5K_QUEUE_MISC(queue),
 					AR5K_QCU_MISC_FRSHED_DBA_GT |
 					AR5K_QCU_MISC_CBREXP_BCN |
 					AR5K_QCU_MISC_BCN_ENABLE);
 
-				AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_DFS_MISC(queue),
+				AR5K_REG_ENABLE_BITS(hal,
+					AR5K_QUEUE_DFS_MISC(queue),
 					(AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
 					AR5K_DCU_MISC_ARBLOCK_CTL_S) |
 					AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
@@ -3594,7 +3571,7 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 		ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts,
 			AR5K_SIMR0_QCU_TXOK) |
 			AR5K_REG_SM(hal->ah_txq_interrupts,
-				AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
+			AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
 		ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts,
 			AR5K_SIMR1_QCU_TXERR), AR5K_SIMR1);
 		ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts,
@@ -3651,8 +3628,8 @@ ath5k_hw_get_slot_time(struct ath_hw *hal)
 {
 	AR5K_TRACE;
 	if (hal->ah_version == AR5K_AR5210)
-		return (ath5k_hw_clocktoh(ath5k_hw_reg_read(hal, AR5K_SLOT_TIME) &
-		    0xffff, hal->ah_turbo));
+		return (ath5k_hw_clocktoh(ath5k_hw_reg_read(hal,
+				AR5K_SLOT_TIME) & 0xffff, hal->ah_turbo));
 	else
 		return ath5k_hw_reg_read(hal, AR5K_DCU_GBL_IFS_SLOT) & 0xffff;
 }
@@ -4120,29 +4097,24 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal,
 	 * Frame receive status
 	 */
 	desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
-	    AR5K_OLD_RX_DESC_STATUS0_DATA_LEN;
-	desc->ds_us.rx.rs_rssi =
-	    AR5K_REG_MS(rx_status->rx_status_0,
+		AR5K_OLD_RX_DESC_STATUS0_DATA_LEN;
+	desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
 	    	AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL);
-	desc->ds_us.rx.rs_rate =
-	    AR5K_REG_MS(rx_status->rx_status_0,
+	desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
 	    	AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE);
 	desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
-	    AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA;
+		AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA;
 	desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
-	    AR5K_OLD_RX_DESC_STATUS0_MORE;
-	desc->ds_us.rx.rs_tstamp =
-	    AR5K_REG_MS(rx_status->rx_status_1,
+		AR5K_OLD_RX_DESC_STATUS0_MORE;
+	desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
 	    	AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
 	desc->ds_us.rx.rs_status = 0;
 
 	/*
 	 * Key table status
 	 */
-	if (rx_status->rx_status_1 &
-	    AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID)
-		desc->ds_us.rx.rs_keyix =
-		    AR5K_REG_MS(rx_status->rx_status_1,
+	if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID)
+		desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
 		    	AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX);
 	else
 		desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID;
@@ -4150,10 +4122,9 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal,
 	/*
 	 * Receive/descriptor errors
 	 */
-	if ((rx_status->rx_status_1 &
-	AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
-		if (rx_status->rx_status_1 &
-				AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR)
+	if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK)
+			== 0) {
+		if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR)
 			desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC;
 
 		if (rx_status->rx_status_1 &
@@ -4201,19 +4172,16 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal,
 	 */
 	desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
 		AR5K_NEW_RX_DESC_STATUS0_DATA_LEN;
-	desc->ds_us.rx.rs_rssi =
-		AR5K_REG_MS(rx_status->rx_status_0,
-			AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL);
-	desc->ds_us.rx.rs_rate =
-		AR5K_REG_MS(rx_status->rx_status_0,
-			AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE);
+	desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
+		AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL);
+	desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
+		AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE);
 	desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
 		AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA;
 	desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
 		AR5K_NEW_RX_DESC_STATUS0_MORE;
-	desc->ds_us.rx.rs_tstamp =
-		AR5K_REG_MS(rx_status->rx_status_1,
-			AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
+	desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
+		AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
 	desc->ds_us.rx.rs_status = 0;
 
 	/*
@@ -4244,8 +4212,7 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal,
 				AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
 			desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT;
 
-		if (rx_status->rx_status_1 &
-				AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR)
+		if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR)
 			desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC;
 	}
 
@@ -4253,8 +4220,6 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal,
 }
 
 
-
-
 /****************\
   GPIO Functions
 \****************/
@@ -4275,8 +4240,7 @@ void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state)
 		AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG,
 			AR5K_PCICFG_LEDMODE |  AR5K_PCICFG_LED);
 	else
-		AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG,
-				AR5K_PCICFG_LED);
+		AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_LED);
 
 	/*
 	 * Some blinking values, define at your wish
@@ -4284,28 +4248,23 @@ void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state)
 	switch (state) {
 	case AR5K_LED_SCAN:
 	case AR5K_LED_AUTH:
-		led = AR5K_PCICFG_LEDMODE_PROP |
-			AR5K_PCICFG_LED_PEND;
-		led_5210 = AR5K_PCICFG_LED_PEND|
-			AR5K_PCICFG_LED_BCTL;
+		led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_PEND;
+		led_5210 = AR5K_PCICFG_LED_PEND | AR5K_PCICFG_LED_BCTL;
 		break;
 
 	case AR5K_LED_INIT:
-		led = AR5K_PCICFG_LEDMODE_PROP |
-			AR5K_PCICFG_LED_NONE;
+		led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_NONE;
 		led_5210 = AR5K_PCICFG_LED_PEND;
 		break;
 
 	case AR5K_LED_ASSOC:
 	case AR5K_LED_RUN:
-		led = AR5K_PCICFG_LEDMODE_PROP |
-			AR5K_PCICFG_LED_ASSOC;
+		led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_ASSOC;
 		led_5210 = AR5K_PCICFG_LED_ASSOC;
 		break;
 
 	default:
-		led = AR5K_PCICFG_LEDMODE_PROM |
-			AR5K_PCICFG_LED_NONE;
+		led = AR5K_PCICFG_LEDMODE_PROM | AR5K_PCICFG_LED_NONE;
 		led_5210 = AR5K_PCICFG_LED_PEND;
 		break;
 	}
@@ -4373,7 +4332,7 @@ int ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val)
 		return -EINVAL;
 
 	/* GPIO output magic */
-	data =  ath5k_hw_reg_read(hal, AR5K_GPIODO);
+	data = ath5k_hw_reg_read(hal, AR5K_GPIODO);
 
 	data &= ~(1 << gpio);
 	data |= (val & 1) << gpio;
@@ -4399,9 +4358,9 @@ void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio,
 	 * Set the GPIO interrupt
 	 */
 	data = (ath5k_hw_reg_read(hal, AR5K_GPIOCR) &
-	    ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH |
-	    AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) |
-	    (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA);
+		~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH |
+		AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) |
+		(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA);
 
 	ath5k_hw_reg_write(hal, interrupt_level ? data :
 		(data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR);
@@ -4413,8 +4372,6 @@ void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio,
 }
 
 
-
-
 /*********************************\
  Regulatory Domain/Channels Setup
 \*********************************/
@@ -4489,7 +4446,8 @@ static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
 /*
  * Set channel on RF5110
  */
-static int ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
+static int ath5k_hw_rf5110_channel(struct ath_hw *hal,
+		struct ieee80211_channel *channel)
 {
 	u32 data;
 
@@ -4687,7 +4645,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath_hw *hal,
 	 * Disable beacons and RX/TX queues, wait
 	 */
 	AR5K_REG_ENABLE_BITS(hal, AR5K_DIAG_SW_5210,
-	    AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
+		AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
 	beacon = ath5k_hw_reg_read(hal, AR5K_BEACON_5210);
 	ath5k_hw_reg_write(hal, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
 
@@ -4920,16 +4878,15 @@ static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
 
 	for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
 		last = (position + left > 8) ? 8 : position + left;
-		mask = (((1 << last) - 1) ^ ((1 << position) - 1)) <<
-		    (col * 8);
+		mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
 
 		if (set == true) {
 			rf[entry] &= ~mask;
 			rf[entry] |= ((data << position) << (col * 8)) & mask;
 			data >>= (8 - position);
 		} else {
-			data = (((rf[entry] & mask) >> (col * 8)) >>
-			    position) << shift;
+			data = (((rf[entry] & mask) >> (col * 8)) >> position)
+				<< shift;
 			shift += last - position;
 		}
 
@@ -4987,20 +4944,20 @@ static bool ath5k_hw_rfregs_gain_readback(struct ath_hw *hal)
 	rf = hal->ah_rf_banks;
 
 	if (hal->ah_radio == AR5K_RF5111) {
-		step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
-		    0, 6, 37, 0, false);
+		step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 6, 37, 0,
+				false);
 		level[0] = 0;
 		level[1] = (step == 0x3f) ? 0x32 : step + 4;
 		level[2] = (step != 0x3f) ? 0x40 : level[0];
 		level[3] = level[2] + 0x32;
 
 		hal->ah_gain.g_high = level[3] -
-		    (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
+			(step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
 		hal->ah_gain.g_low = level[0] +
-		    (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
+			(step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
 	} else {
-		mix = ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
-		    0, 1, 36, 0, false);
+		mix = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0,
+				false);
 		level[0] = level[2] = 0;
 
 		if (mix == 1) {
@@ -5011,10 +4968,10 @@ static bool ath5k_hw_rfregs_gain_readback(struct ath_hw *hal)
 		}
 	}
 
-	return ((hal->ah_gain.g_current >= level[0] &&
-	    hal->ah_gain.g_current <= level[1]) ||
-	    (hal->ah_gain.g_current >= level[2] &&
-	    hal->ah_gain.g_current <= level[3]));
+	return (hal->ah_gain.g_current >= level[0] &&
+			hal->ah_gain.g_current <= level[1]) ||
+		(hal->ah_gain.g_current >= level[2] &&
+			hal->ah_gain.g_current <= level[3]);
 }
 
 static s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal)
@@ -5063,10 +5020,8 @@ static s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal)
 done:
 #ifdef AR5K_DEBUG
 	AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n",
-	    ret,
-	    hal->ah_gain.g_step_idx,
-	    hal->ah_gain.g_current,
-	    hal->ah_gain.g_target);
+		ret, hal->ah_gain.g_step_idx, hal->ah_gain.g_current,
+		hal->ah_gain.g_target);
 #endif
 
 	return ret;
@@ -5120,9 +5075,10 @@ static int ath5k_hw_rf5111_rfregs(struct ath_hw *hal,
 		struct ieee80211_channel *channel, unsigned int mode)
 {
 	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
-	const unsigned int rf_size = ARRAY_SIZE(rf5111_rf);
 	u32 *rf;
-	int i, obdb = -1, bank = -1;
+	const unsigned int rf_size = ARRAY_SIZE(rf5111_rf);
+	unsigned int i;
+	int obdb = -1, bank = -1;
 	u32 ee_mode;
 
 	AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
@@ -5165,10 +5121,10 @@ static int ath5k_hw_rf5111_rfregs(struct ath_hw *hal,
 	} else {
 		/* For 11a, Turbo and XR */
 		ee_mode = AR5K_EEPROM_MODE_11A;
-		obdb = channel->freq >= 5725 ? 3 :
-		    (channel->freq >= 5500 ? 2 :
+		obdb =	 channel->freq >= 5725 ? 3 :
+			(channel->freq >= 5500 ? 2 :
 			(channel->freq >= 5260 ? 1 :
-			    (channel->freq > 4000 ? 0 : -1)));
+			 (channel->freq > 4000 ? 0 : -1)));
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
 				ee->ee_pwd_84, 1, 51, 3, true))
@@ -5219,12 +5175,12 @@ static int ath5k_hw_rf5111_rfregs(struct ath_hw *hal,
 static int ath5k_hw_rf5112_rfregs(struct ath_hw *hal,
 		struct ieee80211_channel *channel, unsigned int mode)
 {
+	const struct ath5k_ini_rf *rf_ini;
 	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
-	unsigned int rf_size;
 	u32 *rf;
-	int i, obdb = -1, bank = -1;
+	unsigned int rf_size, i;
+	int obdb = -1, bank = -1;
 	u32 ee_mode;
-	const struct ath5k_ini_rf *rf_ini;
 
 	AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
 
@@ -5338,10 +5294,10 @@ static void ath5k_hw_ar5211_rfregs(struct ath_hw *hal,
 
 	if (freq == AR5K_INI_RFGAIN_5GHZ) {
 		/* For 11a and Turbo */
-		obdb = channel->freq >= 5725 ? 3 :
+		obdb =	 channel->freq >= 5725 ? 3 :
 			(channel->freq >= 5500 ? 2 :
-				(channel->freq >= 5260 ? 1 :
-					(channel->freq > 4000 ? 0 : -1)));
+			(channel->freq >= 5260 ? 1 :
+			(channel->freq >  4000 ? 0 : -1)));
 	}
 
 	ob = ee->ee_ob[ee_mode][obdb];
@@ -5375,7 +5331,7 @@ static void ath5k_hw_ar5211_rfregs(struct ath_hw *hal,
 bool
 ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq)
 {
-	int i;
+	unsigned int i;
 
 	switch (phy) {
 	case AR5K_INI_PHY_5111:
@@ -5449,10 +5405,11 @@ done:
 /*
  * Initialize the tx power table (not fully implemented)
  */
-static void ath5k_txpower_table(struct ath_hw *hal, struct ieee80211_channel *channel, s16 max_power)
+static void ath5k_txpower_table(struct ath_hw *hal,
+		struct ieee80211_channel *channel, s16 max_power)
 {
-	u16 txpower, *rates;
 	unsigned int i, min, max, n;
+	u16 txpower, *rates;
 
 	rates = hal->ah_txpower.txp_rates;
 
@@ -5487,7 +5444,8 @@ static void ath5k_txpower_table(struct ath_hw *hal, struct ieee80211_channel *ch
  * Set transmition power
  */
 static int /*O.K. - txpower_table is unimplemented so this doesn't work*/
-ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int txpower)
+ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel,
+		unsigned int txpower)
 {
 	bool tpc = hal->ah_txpower.txp_tpc;
 	unsigned int i;
@@ -5510,8 +5468,8 @@ ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned
 	 */
 	for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
 		ath5k_hw_reg_write(hal,
-		      ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16)
-		    | ((((hal->ah_txpower.txp_pcdac[(i << 1)    ] << 8) | 0xff) & 0xffff)      ),
+			((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) |
+			(((hal->ah_txpower.txp_pcdac[(i << 1)    ] << 8) | 0xff) & 0xffff),
 			AR5K_PHY_PCDAC_TXPOWER(i));
 	}
 
@@ -5724,8 +5682,7 @@ ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid,
 	AR5K_TRACE;
 	if (hal->ah_version == AR5K_AR5210) {
 		AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1,
-			AR5K_STA_ID1_NO_PSPOLL |
-			AR5K_STA_ID1_DEFAULT_ANTENNA);
+			AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
 		return true;
 	}
 
@@ -5738,8 +5695,7 @@ ath5k_hw_disable_pspoll(struct ath_hw *hal)
 	AR5K_TRACE;
 	if (hal->ah_version == AR5K_AR5210) {
 		AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1,
-			AR5K_STA_ID1_NO_PSPOLL |
-			AR5K_STA_ID1_DEFAULT_ANTENNA);
+			AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
 		return true;
 	}
 

commit d7a430a90058a987923fce5d0a4ecb27d3edec45
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Tue Jul 17 22:27:35 2007 +0200

    allow AR5K_DEBUG

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 9cd49fc..f74fddc 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -410,7 +410,7 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc,
 	ath5k_hw_set_opmode(hal);
 		
 #ifdef AR5K_DEBUG
-	hal->ah_dump_state(hal);
+	ath5k_hw_dump_state(hal);
 #endif
 
 	/*
@@ -5601,8 +5601,6 @@ ath5k_hw_dump_state(struct ath_hw *hal)
 	AR5K_PRINT_REGISTER(DCU_FP);
 	AR5K_PRINT_REGISTER(DCU_TXP);
 	AR5K_PRINT_REGISTER(DCU_TX_FILTER);
-	AR5K_PRINT_REGISTER(RC);
-	AR5K_PRINT_REGISTER(SCR);
 	AR5K_PRINT_REGISTER(INTPEND);
 	AR5K_PRINT_REGISTER(PCICFG);
 	AR5K_PRINT_REGISTER(GPIOCR);
@@ -5638,8 +5636,6 @@ ath5k_hw_dump_state(struct ath_hw *hal)
 	AR5K_PRINT_REGISTER(FCS_FAIL);
 	AR5K_PRINT_REGISTER(BEACON_CNT);
 	AR5K_PRINT_REGISTER(TSF_PARM);
-	AR5K_PRINT_REGISTER(RATE_DUR_0);
-	AR5K_PRINT_REGISTER(KEYTABLE_0);
 	AR5K_PRINT("\n");
 
 	AR5K_PRINT("PHY registers:\n");
@@ -5657,7 +5653,6 @@ ath5k_hw_dump_state(struct ath_hw *hal)
 	AR5K_PRINT_REGISTER(PHY_PAPD_PROBE);
 	AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE1);
 	AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE2);
-	AR5K_PRINT_REGISTER(PHY_FC);
 	AR5K_PRINT_REGISTER(PHY_RADAR);
 	AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_0);
 	AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_1);

commit cca3b8ecb67d8ee86b7287f3990915b72d3d618a
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Tue Jul 17 22:15:33 2007 +0200

    remove double included linux/pci

diff --git a/ath5k_hw.c b/ath5k_hw.c
index f84c94c..9cd49fc 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -22,8 +22,6 @@
 
 #include <linux/pci.h>
 
-#include <linux/pci.h>
-
 #include "ath5k.h"
 #include "ath5k_reg.h"
 

commit 89e9066109c0f7313198d0e10c5af01a70755493
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Tue Jul 17 22:15:18 2007 +0200

    remove unused fucntions

diff --git a/ath5k_hw.c b/ath5k_hw.c
index ef8b960..f84c94c 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -22,7 +22,6 @@
 
 #include <linux/pci.h>
 
-#include <asm/unaligned.h>
 #include <linux/pci.h>
 
 #include "ath5k.h"
@@ -227,26 +226,6 @@ static inline void ath5k_hw_reg_write(struct ath_hw *hal, u32 val, u16 reg)
 	writel(val, hal->ah_sh + reg);
 }
 
-static inline __u16 ath5k_hw_unaligned_read_16(__le16 *p)
-{
-	return le16_to_cpu(get_unaligned(p));
-}
-
-static inline void ath5k_hw_unaligned_write_16(__u16 v, __le16* p)
-{
-	put_unaligned(cpu_to_le16(v), p);
-}
-
-static inline __u32 ath5k_hw_unaligned_read_32(__le32 *p)
-{
-	return le32_to_cpu(get_unaligned(p));
-}
-
-static inline void ath5k_hw_unaligned_write_32(__u32 v, __le32 *p)
-{
-	put_unaligned(cpu_to_le32(v), p);
-}
-
 /*
  * Check if a register write has been completed
  */

commit 20955a02d7ddeef222c7811e31d16be148a45f9c
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Tue Jul 17 08:37:20 2007 +0200

    make some functions static

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 6f17542..ef8b960 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -14,12 +14,10 @@
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
- * $Id$
  */
 
 /*
  * HAL interface for Atheros Wireless LAN devices.
- * (Please have a look at ar5xxx.h for further information)
  */
 
 #include <linux/pci.h>
@@ -124,7 +122,7 @@ static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN;
  * Calculate transmition time of a frame
  * TODO: Left here for combatibility, change it in ath5k
  */
-u16 /*TODO: Is this really hardware dependent ?*/
+static u16 /*TODO: Is this really hardware dependent ?*/
 ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates,
     u32 frame_length, u16 rate_index, bool short_preamble)
 {
@@ -1976,8 +1974,7 @@ static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data)
 	return -EIO;
 }
 
-u16
-ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode)
+static u16 ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode)
 {
 	u16 val;
 
@@ -2004,8 +2001,8 @@ ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode)
 /*
  * Read antenna infos from eeprom
  */
-int
-ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode)
+static int ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset,
+		unsigned int mode)
 {
 	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
 	u32 o = *offset;
@@ -2063,8 +2060,8 @@ ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode)
 /*
  * Read supported modes from eeprom
  */
-int
-ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode)
+static int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset,
+		unsigned int mode)
 {
 	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
 	u32 o = *offset;
@@ -4920,7 +4917,7 @@ ath5k_hw_get_def_antenna(struct ath_hw *hal)
 	return false; /*XXX: What do we return for 5210 ?*/
 }
 
-unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
+static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
 		u32 first, u32 col, bool set)
 {
 	u32 mask, entry, last, data, shift, position;
@@ -4967,8 +4964,7 @@ unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
 	return data;
 }
 
-u32
-ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal)
+static u32 ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal)
 {
 	u32 mix, step;
 	u32 *rf;
@@ -5003,14 +4999,13 @@ ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal)
 	return hal->ah_gain.g_f_corr;
 }
 
-bool
-ath5k_hw_rfregs_gain_readback(struct ath_hw *hal)
+static bool ath5k_hw_rfregs_gain_readback(struct ath_hw *hal)
 {
 	u32 step, mix, level[4];
 	u32 *rf;
 
 	if (hal->ah_rf_banks == NULL)
-		return 0;
+		return false;
 
 	rf = hal->ah_rf_banks;
 
@@ -5045,7 +5040,7 @@ ath5k_hw_rfregs_gain_readback(struct ath_hw *hal)
 	    hal->ah_gain.g_current <= level[3]));
 }
 
-s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal)
+static s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal)
 {
 	const struct ath5k_gain_opt *go;
 	int ret = 0;

commit 3f73797a653e5ae300443a809d9de4a5f4f19c21
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Tue Jul 17 08:06:18 2007 +0200

    isr optimisation (likely/unlikely)

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 963b695..6f17542 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -1737,7 +1737,7 @@ int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask)
 	 */
 	if (hal->ah_version == AR5K_AR5210) {
 		data = ath5k_hw_reg_read(hal, AR5K_ISR);
-		if (data == AR5K_INT_NOCARD) {
+		if (unlikely(data == AR5K_INT_NOCARD)) {
 			*interrupt_mask = data;
 			return -ENODEV;
 		}
@@ -1753,7 +1753,7 @@ int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask)
 	 */
 	*interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr;
 
-	if (data == AR5K_INT_NOCARD)
+	if (unlikely(data == AR5K_INT_NOCARD))
 		return -ENODEV;
 
 	if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR))
@@ -1764,11 +1764,11 @@ int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask)
 
 	if (hal->ah_version != AR5K_AR5210) {
 		/*HIU = Host Interface Unit (PCI etc)*/
-		if (data & (AR5K_ISR_HIUERR))
+		if (unlikely(data & (AR5K_ISR_HIUERR)))
 			*interrupt_mask |= AR5K_INT_FATAL;
 
 		/*Beacon Not Ready*/
-		if (data & (AR5K_ISR_BNR))
+		if (unlikely(data & (AR5K_ISR_BNR)))
 			*interrupt_mask |= AR5K_INT_BNR;
 	}
 
@@ -1784,7 +1784,7 @@ int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask)
 	 * In case we didn't handle anything,
 	 * print the register value.
 	 */
-	if (*interrupt_mask == 0 && printk_ratelimit())
+	if (unlikely(*interrupt_mask == 0 && net_ratelimit()))
 		AR5K_PRINTF("0x%08x\n", data);
 
 	return 0;
@@ -3976,7 +3976,7 @@ static int ath5k_hw_proc_2word_tx_status(struct ath_hw *hal,
 	tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[0];
 
 	/* No frame has been send or error */
-	if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)
+	if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
 		return -EINPROGRESS;
 
 	/*
@@ -4027,7 +4027,7 @@ static int ath5k_hw_proc_4word_tx_status(struct ath_hw *hal,
 	tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2];
 
 	/* No frame has been send or error */
-	if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)
+	if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
 		return -EINPROGRESS;
 
 	/*
@@ -4118,7 +4118,7 @@ int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc,
 
 	/* Setup descriptor */
 	rx_desc->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
-	if (rx_desc->rx_control_1 != size)
+	if (unlikely(rx_desc->rx_control_1 != size))
 		return -EINVAL;
 
 	if (flags & AR5K_RXDESC_INTREQ)
@@ -4138,7 +4138,8 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal,
 	rx_status = (struct ath5k_hw_old_rx_status*)&desc->ds_hw[0];
 
 	/* No frame received / not ready */
-	if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE) == 0)
+	if (unlikely((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE)
+				== 0))
 		return -EINPROGRESS;
 
 	/*
@@ -4217,7 +4218,8 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal,
 	rx_err = (struct ath5k_hw_rx_error*)&desc->ds_hw[0];
 
 	/* No frame received / not ready */
-	if ((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE) == 0)
+	if (unlikely((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE)
+				== 0))
 		return -EINPROGRESS;
 
 	/*

commit 5875b4d8b6f3cbfd5498edecdf8b20cc3f339522
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Mon Jul 16 09:01:32 2007 +0200

    some capability cleanup

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 00faf4d..963b695 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -5698,11 +5698,6 @@ int ath5k_hw_get_capability(struct ath_hw *hal,
 	AR5K_TRACE;
 
 	switch (cap_type) {
-	case AR5K_CAP_REG_DMN:
-		if (result){
-			*result = ath5k_get_regdomain(hal);
-			goto yes;
-		}
 	case AR5K_CAP_NUM_TXQUEUES: 
 		if (result) {
 			if (hal->ah_version == AR5K_AR5210)
@@ -5743,15 +5738,6 @@ int ath5k_hw_get_capability(struct ath_hw *hal,
 	
 }
 
-int ath5k_hw_set_capability(struct ath_hw *hal,
-		enum ath5k_capability_type cap_type,
-		u32 capability, u32 setting)
-{
-	AR5K_TRACE;
-
-	return 0;
-}
-
 bool
 ath5k_hw_query_pspoll_support(struct ath_hw *hal)
 {

commit 77ed58d5f9f022d808eac8dee773d8adf8d8155a
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Mon Jul 16 08:57:25 2007 +0200

    hal: channels cleanup (remove ath_hal_mhz2ieee and co.)

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 4460105..00faf4d 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -4444,43 +4444,9 @@ void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio,
 \*********************************/
 
 /*
- * Following 2 functions come from net80211 
- * TODO: These do not belong here, they have nothing
- * to do with hw. I left them here temporarily for
- * combatibility.
- * M.F.
- */
-
-/*
- * Convert MHz frequency to IEEE channel number.
- */
-unsigned int
-ath_hal_mhz2ieee(unsigned int freq, u_int flags)
-{
-	if (flags & CHANNEL_2GHZ) {	/* 2GHz band */
-		if (freq == 2484)		/* Japan */
-			return 14;
-		/* don't number non-IEEE channels unless we do channel tests */
-		if ((freq >= 2412) && (freq < 2484))
-			return (freq - 2407) / 5;
-		if (CHAN_DEBUG == 1) /* 15-26 */
-			return ((freq - 2512)/20) + 15;
-		return 0;
-	} else if (flags & CHANNEL_5GHZ)	{	/* 5Ghz band */
-		/* don't number non-IEEE channels unless we do channel tests */
-		if (((freq >= 5150) && (freq <= 5825))|| CHAN_DEBUG == 1)
-			return (freq - 5000) / 5;
-		return 0;
-	} else
-		/* something is fishy, don't do anything */
-		return 0;
-}
-
-/*
  * Check if a channel is supported
  */
-bool
-ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags)
+bool ath5k_channel_ok(struct ath_hw *hal, u16 freq, unsigned int flags)
 {
 	/* Check if the channel is in our supported range */
 	if (flags & CHANNEL_2GHZ) {
@@ -4495,8 +4461,7 @@ ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags)
 	return false;
 }
 
-u16
-ath5k_get_regdomain(struct ath_hw *hal)
+u16 ath5k_get_regdomain(struct ath_hw *hal)
 {
 	u16 regdomain;
 	enum ieee80211_regdomain ieee_regdomain;
@@ -4539,8 +4504,8 @@ static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
 	 * newer chipsets like the AR5212A who have a completely
 	 * different RF/PHY part.
 	 */
-	athchan = (ath5k_hw_bitswap((ath_hal_mhz2ieee(channel->freq,
-		channel->val) - 24) / 2, 5) << 1) | (1 << 6) | 0x1;
+	athchan = (ath5k_hw_bitswap((channel->chan - 24) / 2, 5) << 1) |
+		(1 << 6) | 0x1;
 
 	return athchan;
 }
@@ -4599,7 +4564,7 @@ static int ath5k_hw_rf5111_channel(struct ath_hw *hal,
 		struct ieee80211_channel *channel)
 {
 	struct ath5k_athchan_2ghz ath_channel_2ghz;
-	unsigned int ieee_channel, ath_channel;
+	unsigned int ath_channel = channel->chan;
 	u32 data0, data1, clock;
 	int ret;
 
@@ -4607,12 +4572,10 @@ static int ath5k_hw_rf5111_channel(struct ath_hw *hal,
 	 * Set the channel on the RF5111 radio
 	 */
 	data0 = data1 = 0;
-	ath_channel = ieee_channel = ath_hal_mhz2ieee(channel->freq,
-			channel->val);
 
 	if (channel->val & CHANNEL_2GHZ) {
 		/* Map 2GHz channel to 5GHz Atheros channel ID */
-		ret = ath5k_hw_rf5111_chan2athchan(ieee_channel,
+		ret = ath5k_hw_rf5111_chan2athchan(channel->chan,
 				&ath_channel_2ghz);
 		if (ret)
 			return ret;

commit eed257a53095c0a9c56c8c42f9f8595736fe7cc0
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Mon Jul 16 08:44:51 2007 +0200

    hal: gpio cleanup

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 121d464..4460105 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -4286,8 +4286,7 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal,
 /*
  * Set led state
  */
-void
-ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state)
+void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state)
 {
 	u32 led;
 	/*5210 has different led mode handling*/
@@ -4345,79 +4344,74 @@ ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state)
 /*
  * Set GPIO outputs
  */
-bool
-ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio)
+int ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio)
 {
 	AR5K_TRACE;
 	if (gpio > AR5K_NUM_GPIO)
-		return false;
+		return -EINVAL;
 
 	ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_GPIOCR) &~
 		AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR);
 
-	return true;
+	return 0;
 }
 
 /*
  * Set GPIO inputs
  */
-bool
-ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio)
+int ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio)
 {
 	AR5K_TRACE;
 	if (gpio > AR5K_NUM_GPIO)
-		return false;
+		return -EINVAL;
 
 	ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_GPIOCR) &~
 		AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR);
 
-	return true;
+	return 0;
 }
 
 /*
  * Get GPIO state
  */
-u32
-ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio)
+u32 ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio)
 {
 	AR5K_TRACE;
 	if (gpio > AR5K_NUM_GPIO)
 		return 0xffffffff;
 
 	/* GPIO input magic */
-	return (((ath5k_hw_reg_read(hal, AR5K_GPIODI) &
-	    AR5K_GPIODI_M) >> gpio) & 0x1);
+	return ((ath5k_hw_reg_read(hal, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) &
+		0x1;
 }
 
 /*
  * Set GPIO state
  */
-bool
-ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val)
+int ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val)
 {
 	u32 data;
 	AR5K_TRACE;
 
 	if (gpio > AR5K_NUM_GPIO)
-		return false;
+		return -EINVAL;
 
 	/* GPIO output magic */
 	data =  ath5k_hw_reg_read(hal, AR5K_GPIODO);
 
 	data &= ~(1 << gpio);
-	data |= (val&1) << gpio;
+	data |= (val & 1) << gpio;
 
 	ath5k_hw_reg_write(hal, data, AR5K_GPIODO);
 
-	return true;
+	return 0;
 }
 
 /*
  * Initialize the GPIO interrupt (RFKill switch)
  */
-void
-ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio,
-    u32 interrupt_level)
+void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio,
+		u32 interrupt_level)
 {
 	u32 data;
 

commit a1091593168be19a255d879254ab39314c848d84
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Sun Jul 15 17:29:59 2007 +0200

    calibration

diff --git a/ath5k_hw.c b/ath5k_hw.c
index 2b8cce7..121d464 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -66,6 +66,16 @@ static int ath5k_hw_get_capabilities(struct ath_hw *);
 static int ath5k_eeprom_init(struct ath_hw *);
 static int ath5k_eeprom_read_mac(struct ath_hw *, u8 *);
 
+static int ath5k_hw_channel(struct ath_hw *, struct ieee80211_channel *);
+static int ath5k_hw_rfregs(struct ath_hw *, struct ieee80211_channel *,
+		unsigned int);
+static int ath5k_hw_rf5111_rfregs(struct ath_hw *, struct ieee80211_channel *,
+		unsigned int);
+static int ath5k_hw_rf5112_rfregs(struct ath_hw *, struct ieee80211_channel *,
+		unsigned int);
+static void ath5k_hw_ar5211_rfregs(struct ath_hw *, struct ieee80211_channel *,
+		unsigned int, unsigned int);
+
 /*
  * Initial register dumps
  */
@@ -983,9 +993,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 		 * Write RF registers
 		 * TODO:Does this work on 5211 (5111) ?
 		 */
-		if (ath5k_hw_rfregs(hal, channel, mode) == false) {
-			return -EINPROGRESS;
-		}
+		ret = ath5k_hw_rfregs(hal, channel, mode);
+		if (ret)
+			return ret;
 
 		/*
 		 * Configure additional registers
@@ -1137,8 +1147,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 	/*
 	 * Set channel and calibrate the PHY
 	 */
-	if (ath5k_hw_channel(hal, channel) == false)
-		return -EIO;
+	ret = ath5k_hw_channel(hal, channel);
+	if (ret)
+		return ret;
 
 	/*
 	 * Enable the PHY and wait until completion
@@ -4522,51 +4533,9 @@ ath5k_get_regdomain(struct ath_hw *hal)
 \*************************/
 
 /*
- * Set a channel on the radio chip
- */
-bool
-ath5k_hw_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
-{
-	bool ret;
-
-	/*
-	 * Check bounds supported by the PHY
-	 * (don't care about regulation restrictions at this point)
-	 */
-	if ((channel->freq < hal->ah_capabilities.cap_range.range_2ghz_min ||
-	    channel->freq > hal->ah_capabilities.cap_range.range_2ghz_max) &&
-	    (channel->freq < hal->ah_capabilities.cap_range.range_5ghz_min ||
-	    channel->freq > hal->ah_capabilities.cap_range.range_5ghz_max)) {
-		AR5K_PRINTF("channel out of supported range (%u MHz)\n",
-		    channel->freq);
-		return false;
-	}
-
-	/*
-	 * Set the channel and wait
-	 */
-	if (hal->ah_radio == AR5K_RF5110)
-		ret = ath5k_hw_rf5110_channel(hal, channel);
-	else if (hal->ah_radio == AR5K_RF5111)
-		ret = ath5k_hw_rf5111_channel(hal, channel);
-	else
-		ret = ath5k_hw_rf5112_channel(hal, channel);
-
-	if (ret == false)
-		return ret;
-
-	hal->ah_current_channel.freq = channel->freq;
-	hal->ah_current_channel.val = channel->val;
-	hal->ah_turbo = channel->val == CHANNEL_T ? true : false;
-
-	return true;
-}
-
-/*
  * Convertion needed for RF5110
  */
-u32
-ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
+static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
 {
 	u32 athchan;
 
@@ -4577,8 +4546,7 @@ ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
 	 * different RF/PHY part.
 	 */
 	athchan = (ath5k_hw_bitswap((ath_hal_mhz2ieee(channel->freq,
-	    channel->val) - 24) / 2, 5) << 1) |
-	    (1 << 6) | 0x1;
+		channel->val) - 24) / 2, 5) << 1) | (1 << 6) | 0x1;
 
 	return athchan;
 }
@@ -4586,8 +4554,7 @@ ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
 /*
  * Set channel on RF5110
  */
-bool
-ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
+static int ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
 {
 	u32 data;
 
@@ -4599,14 +4566,14 @@ ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
 	ath5k_hw_reg_write(hal, 0, AR5K_RF_BUFFER_CONTROL_0);
 	mdelay(1);
 
-	return true;
+	return 0;
 }
 
 /*
  * Convertion needed for 5111
  */
-bool
-ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athchan)
+static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
+		struct ath5k_athchan_2ghz *athchan)
 {
 	int channel;
 
@@ -4626,33 +4593,35 @@ ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athch
 		athchan->a2_athchan = ((channel - 14) * 4) + 132;
 		athchan->a2_flags = 0x46;
 	} else
-		return false;
+		return -EINVAL;
 
-	return true;
+	return 0;
 }
 
 /*
  * Set channel on 5111
  */
-bool
-ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
+static int ath5k_hw_rf5111_channel(struct ath_hw *hal,
+		struct ieee80211_channel *channel)
 {
+	struct ath5k_athchan_2ghz ath_channel_2ghz;
 	unsigned int ieee_channel, ath_channel;
 	u32 data0, data1, clock;
-	struct ath5k_athchan_2ghz ath_channel_2ghz;
+	int ret;
 
 	/*
 	 * Set the channel on the RF5111 radio
 	 */
 	data0 = data1 = 0;
 	ath_channel = ieee_channel = ath_hal_mhz2ieee(channel->freq,
-	    channel->val);
+			channel->val);
 
 	if (channel->val & CHANNEL_2GHZ) {
 		/* Map 2GHz channel to 5GHz Atheros channel ID */
-		if (ath5k_hw_rf5111_chan2athchan(ieee_channel,
-			&ath_channel_2ghz) == false)
-			return false;
+		ret = ath5k_hw_rf5111_chan2athchan(ieee_channel,
+				&ath_channel_2ghz);
+		if (ret)
+			return ret;
 
 		ath_channel = ath_channel_2ghz.a2_athchan;
 		data0 = ((ath5k_hw_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff)
@@ -4674,14 +4643,14 @@ ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
 	ath5k_hw_reg_write(hal, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
 			AR5K_RF_BUFFER_CONTROL_3);
 
-	return true;
+	return 0;
 }
 
 /*
  * Set channel on 5112
  */
-bool
-ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
+static int ath5k_hw_rf5112_channel(struct ath_hw *hal,
+		struct ieee80211_channel *channel)
 {
 	u32 data, data0, data1, data2;
 	u16 c;
@@ -4700,7 +4669,7 @@ ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
 			data0 = ((2 * (c - 672)) - 3040) / 10;
 			data1 = 0;
 		} else
-			return false;
+			return -EINVAL;
 
 		data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
 	} else {
@@ -4714,7 +4683,7 @@ ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
 			data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
 			data2 = ath5k_hw_bitswap(1, 2);
 		} else
-			return false;
+			return -EINVAL;
 	}
 
 	data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
@@ -4722,44 +4691,64 @@ ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
 	ath5k_hw_reg_write(hal, data & 0xff, AR5K_RF_BUFFER);
 	ath5k_hw_reg_write(hal, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
 
-	return true;
+	return 0;
 }
 
 /*
- * Perform a PHY calibration
+ * Set a channel on the radio chip
  */
-bool
-ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel){
+static int ath5k_hw_channel(struct ath_hw *hal,
+		struct ieee80211_channel *channel)
+{
+	int ret;
 
-	bool ret;
+	/*
+	 * Check bounds supported by the PHY
+	 * (don't care about regulation restrictions at this point)
+	 */
+	if ((channel->freq < hal->ah_capabilities.cap_range.range_2ghz_min ||
+	    channel->freq > hal->ah_capabilities.cap_range.range_2ghz_max) &&
+	    (channel->freq < hal->ah_capabilities.cap_range.range_5ghz_min ||
+	    channel->freq > hal->ah_capabilities.cap_range.range_5ghz_max)) {
+		AR5K_PRINTF("channel out of supported range (%u MHz)\n",
+			channel->freq);
+		return -EINVAL;
+	}
 
-	if (hal->ah_radio == AR5K_RF5110)
-		ret = ath5k_hw_rf5110_calibrate(hal,channel);
-	else
-		ret = ath5k_hw_rf511x_calibrate(hal,channel);
+	/*
+	 * Set the channel and wait
+	 */
+	switch (hal->ah_radio) {
+	case AR5K_RF5110:
+		ret = ath5k_hw_rf5110_channel(hal, channel);
+		break;
+	case AR5K_RF5111:
+		ret = ath5k_hw_rf5111_channel(hal, channel);
+		break;
+	default:
+		ret = ath5k_hw_rf5112_channel(hal, channel);
+		break;
+	}
 
-	return ret;
+	if (ret)
+		return ret;
+
+	hal->ah_current_channel.freq = channel->freq;
+	hal->ah_current_channel.val = channel->val;
+	hal->ah_turbo = channel->val == CHANNEL_T ? true : false;
+
+	return 0;
 }
+
 /*
  * Perform a PHY calibration on RF5110
  */
-bool
-ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel)
+static int ath5k_hw_rf5110_calibrate(struct ath_hw *hal,
+		struct ieee80211_channel *channel)
 {
-	bool ret = true;
 	u32 phy_sig, phy_agc, phy_sat, beacon, noise_floor;
 	unsigned int i;
-
-#define AGC_DISABLE	{			\
-	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGC,	\
-		AR5K_PHY_AGC_DISABLE);		\
-	udelay(10);				\
-}
-
-#define AGC_ENABLE	{			\
-	AR5K_REG_DISABLE_BITS(hal, AR5K_PHY_AGC,	\
-	    AR5K_PHY_AGC_DISABLE);		\
-}
+	int ret;
 
 	/*
 	 * Disable beacons and RX/TX queues, wait
@@ -4774,7 +4763,8 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel)
 	/*
 	 * Set the channel (with AGC turned off)
 	 */
-	AGC_DISABLE;
+	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
+	udelay(10);
 	ret = ath5k_hw_channel(hal, channel);
 
 	/*
@@ -4783,9 +4773,9 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel)
 	ath5k_hw_reg_write(hal, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
 	mdelay(1);
 
-	AGC_ENABLE;
+	AR5K_REG_DISABLE_BITS(hal, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
 
-	if (ret == false)
+	if (ret)
 		return ret;
 
 	/*
@@ -4813,44 +4803,42 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel)
 
 	udelay(20);
 
-	AGC_DISABLE;
+	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
+	udelay(10);
 	ath5k_hw_reg_write(hal, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
-	AGC_ENABLE;
+	AR5K_REG_DISABLE_BITS(hal, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
 
 	mdelay(1);
 
 	/*
 	 * Enable calibration and wait until completion
 	 */
-	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL,
-				AR5K_PHY_AGCCTL_CAL);
+	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
 
-	if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
-			AR5K_PHY_AGCCTL_CAL, 0, false)) {
-		AR5K_PRINTF("calibration timeout (%uMHz)\n",
-			channel->freq);
-		ret = false;
-	}
+	ret = ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
+			AR5K_PHY_AGCCTL_CAL, 0, false);
 
 	/* Reset to normal state */
 	ath5k_hw_reg_write(hal, phy_sig, AR5K_PHY_SIG);
 	ath5k_hw_reg_write(hal, phy_agc, AR5K_PHY_AGCCOARSE);
 	ath5k_hw_reg_write(hal, phy_sat, AR5K_PHY_ADCSAT);
 
-	if (ret == false)
-		return false;
+	if (ret) {
+		AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq);
+		return ret;
+	}
 
 	/*
  	 * Enable noise floor calibration and wait until completion
  	 */
-	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL,
-				AR5K_PHY_AGCCTL_NF);
+	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF);
 
-	if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
-			AR5K_PHY_AGCCTL_NF, 0, false)) {
+	ret = ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
+			AR5K_PHY_AGCCTL_NF, 0, false);
+	if (ret) {
 		AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n",
 				channel->freq);
-		return false;
+		return ret;
 	}
 
 	/* Wait until the noise floor is calibrated */
@@ -4858,8 +4846,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel)
 		mdelay(1);
 		noise_floor = ath5k_hw_reg_read(hal, AR5K_PHY_NF);
 
-		if (AR5K_PHY_NF_RVAL(noise_floor) &
-		AR5K_PHY_NF_ACTIVE)
+		if (AR5K_PHY_NF_RVAL(noise_floor) & AR5K_PHY_NF_ACTIVE)
 			noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
 	
 		if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
@@ -4869,10 +4856,9 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel)
 	if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
 		AR5K_PRINTF("noise floor calibration failed (%uMHz)\n",
 			channel->freq);
-		return false;
+		return -EIO;
 	}
 
-
 	/*
 	 * Re-enable RX/TX and beacons
 	 */
@@ -4880,24 +4866,21 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel)
 		AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
 	ath5k_hw_reg_write(hal, beacon, AR5K_BEACON_5210);
 
-#undef AGC_ENABLE
-#undef AGC_DISABLE
-
-	return true;
+	return 0;
 }
 
 /*
  * Perform a PHY calibration on RF5111/5112
  */
-bool
-ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel)
+static int ath5k_hw_rf511x_calibrate(struct ath_hw *hal,
+		struct ieee80211_channel *channel)
 {
 	u32 i_pwr, q_pwr;
 	s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
 	AR5K_TRACE;
 
 	if (hal->ah_calibration == false ||
-	    ath5k_hw_reg_read(hal, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
+			ath5k_hw_reg_read(hal, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
 		goto done;
 
 	hal->ah_calibration = false;
@@ -4915,15 +4898,12 @@ ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel)
 	q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f;
 
 	/* Commit new IQ value */
-	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ,
-		AR5K_PHY_IQ_CORR_ENABLE |
-		((u32)q_coff) |
-		((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
+	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
+		((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
 
- done:
+done:
 	/* Start noise floor calibration */
-	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL,
-		AR5K_PHY_AGCCTL_NF);
+	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF);
 
 	/* Request RF gain */
 	if (channel->val & CHANNEL_5GHZ) {
@@ -4933,7 +4913,23 @@ ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel)
 		hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED;
 	}
 
-	return true;
+	return 0;
+}
+
+/*
+ * Perform a PHY calibration
+ */
+int ath5k_hw_phy_calibrate(struct ath_hw *hal,
+		struct ieee80211_channel *channel)
+{
+	int ret;
+
+	if (hal->ah_radio == AR5K_RF5110)
+		ret = ath5k_hw_rf5110_calibrate(hal, channel);
+	else
+		ret = ath5k_hw_rf511x_calibrate(hal, channel);
+
+	return ret;
 }
 
 bool
@@ -4965,9 +4961,8 @@ ath5k_hw_get_def_antenna(struct ath_hw *hal)
 	return false; /*XXX: What do we return for 5210 ?*/
 }
 
-unsigned int
-ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
-    u32 first, u32 col, bool set)
+unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
+		u32 first, u32 col, bool set)
 {
 	u32 mask, entry, last, data, shift, position;
 	s32 left;
@@ -5091,14 +5086,12 @@ ath5k_hw_rfregs_gain_readback(struct ath_hw *hal)
 	    hal->ah_gain.g_current <= level[3]));
 }
 
-s32
-ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal)
+s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal)
 {
-	int ret = 0;
 	const struct ath5k_gain_opt *go;
+	int ret = 0;
 
-	go = hal->ah_radio == AR5K_RF5111 ?
-	    &rf5111_gain_opt : &rf5112_gain_opt;
+	go = hal->ah_radio == AR5K_RF5111 ? &rf5111_gain_opt : &rf5112_gain_opt;
 
 	hal->ah_gain.g_step = &go->go_step[hal->ah_gain.g_step_idx];
 
@@ -5106,10 +5099,10 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal)
 		if (hal->ah_gain.g_step_idx == 0)
 			return -1;
 		for (hal->ah_gain.g_target = hal->ah_gain.g_current;
-		    hal->ah_gain.g_target >=  hal->ah_gain.g_high &&
-		    hal->ah_gain.g_step_idx > 0;
-		    hal->ah_gain.g_step =
-		    &go->go_step[hal->ah_gain.g_step_idx]) {
+				hal->ah_gain.g_target >=  hal->ah_gain.g_high &&
+				hal->ah_gain.g_step_idx > 0;
+				hal->ah_gain.g_step =
+					&go->go_step[hal->ah_gain.g_step_idx]) {
 			hal->ah_gain.g_target -= 2 *
 			    (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain -
 			    hal->ah_gain.g_step->gos_gain);
@@ -5123,12 +5116,12 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal)
 		if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1))
 			return -2;
 		for (hal->ah_gain.g_target = hal->ah_gain.g_current;
-		    hal->ah_gain.g_target <=  hal->ah_gain.g_low &&
-		    hal->ah_gain.g_step_idx < (go->go_steps_count - 1);
-		    hal->ah_gain.g_step =
-		    &go->go_step[hal->ah_gain.g_step_idx]) {
+				hal->ah_gain.g_target <= hal->ah_gain.g_low &&
+				hal->ah_gain.g_step_idx < go->go_steps_count-1;
+				hal->ah_gain.g_step =
+					&go->go_step[hal->ah_gain.g_step_idx]) {
 			hal->ah_gain.g_target -= 2 *
-			    (go->go_step[++(hal->ah_gain.g_step_idx)].gos_gain -
+			    (go->go_step[++hal->ah_gain.g_step_idx].gos_gain -
 			    hal->ah_gain.g_step->gos_gain);
 		}
 
@@ -5136,7 +5129,7 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal)
 		goto done;
 	}
 
- done:
+done:
 #ifdef AR5K_DEBUG
 	AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n",
 	    ret,
@@ -5151,36 +5144,39 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal)
 /*
  * Initialize RF
  */
-bool
-ath5k_hw_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode)
+static int ath5k_hw_rfregs(struct ath_hw *hal,
+		struct ieee80211_channel *channel, unsigned int mode)
 {
-	ath5k_rfgain_t *func = NULL;
-	bool ret;
+	int (*func)(struct ath_hw *, struct ieee80211_channel *, unsigned int);
+	int ret;
 
-	if (hal->ah_radio == AR5K_RF5111) {
+	switch (hal->ah_radio) {
+	case AR5K_RF5111:
 		hal->ah_rf_banks_size = sizeof(rf5111_rf);
 		func = ath5k_hw_rf5111_rfregs;
-	} else if (hal->ah_radio == AR5K_RF5112) {
+		break;
+	case AR5K_RF5112:
 		if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
 			hal->ah_rf_banks_size = sizeof(rf5112a_rf);
 		else
 		hal->ah_rf_banks_size = sizeof(rf5112_rf);
 		func = ath5k_hw_rf5112_rfregs;
-	} else
-		return false;
+		break;
+	default:
+		return -EINVAL;
+	}
 
 	if (hal->ah_rf_banks == NULL) {
 		/* XXX do extra checks? */
-		if ((hal->ah_rf_banks = kmalloc(hal->ah_rf_banks_size,
-		    GFP_KERNEL)) == NULL) {
+		hal->ah_rf_banks = kmalloc(hal->ah_rf_banks_size, GFP_KERNEL);
+		if (hal->ah_rf_banks == NULL) {
 			AR5K_PRINT("out of memory\n");
-			return false;
+			return -ENOMEM;
 		}
 	}
 
-	ret = (func)(hal, channel, mode);
-
-	if (ret == true)
+	ret = func(hal, channel, mode);
+	if (!ret)
 		hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
 
 	return ret;
@@ -5189,8 +5185,8 @@ ath5k_hw_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned
 /*
  * Initialize RF5111
  */
-bool
-ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode)
+static int ath5k_hw_rf5111_rfregs(struct ath_hw *hal,
+		struct ieee80211_channel *channel, unsigned int mode)
 {
 	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
 	const unsigned int rf_size = ARRAY_SIZE(rf5111_rf);
@@ -5204,10 +5200,9 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un
 
 	/* Copy values to modify them */
 	for (i = 0; i < rf_size; i++) {
-		if (rf5111_rf[i].rf_bank >=
-		    AR5K_RF5111_INI_RF_MAX_BANKS) {
+		if (rf5111_rf[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
 			AR5K_PRINT("invalid bank\n");
-			return false;
+			return -EINVAL;
 		}
 
 		if (bank != rf5111_rf[i].rf_bank) {
@@ -5227,12 +5222,12 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un
 		obdb = 0;
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0],
-			ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
-			return false;
+				ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
+			return -EINVAL;
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0],
-			ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
-			return false;
+				ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
+			return -EINVAL;
 
 		obdb = 1;
 	/* Modify bank 6 */
@@ -5245,38 +5240,38 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un
 			    (channel->freq > 4000 ? 0 : -1)));
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-			ee->ee_pwd_84, 1, 51, 3, true))
-			return false;
+				ee->ee_pwd_84, 1, 51, 3, true))
+			return -EINVAL;
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-			ee->ee_pwd_90, 1, 45, 3, true))
-			return false;
+				ee->ee_pwd_90, 1, 45, 3, true))
+			return -EINVAL;
 	}
 
 	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-		!ee->ee_xpd[ee_mode], 1, 95, 0, true))
-		return false;
+			!ee->ee_xpd[ee_mode], 1, 95, 0, true))
+		return -EINVAL;
 
 	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-		ee->ee_x_gain[ee_mode], 4, 96, 0, true))
-		return false;
+			ee->ee_x_gain[ee_mode], 4, 96, 0, true))
+		return -EINVAL;
 
-	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-		obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
-		return false;
+	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], obdb >= 0 ?
+			ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
+		return -EINVAL;
 
-	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-		obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
-		return false;
+	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], obdb >= 0 ?
+			ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
+		return -EINVAL;
 
 	/* Modify bank 7 */
 	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
-		ee->ee_i_gain[ee_mode], 6, 29, 0, true))
-		return false;
+			ee->ee_i_gain[ee_mode], 6, 29, 0, true))
+		return -EINVAL;
 
 	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
-		ee->ee_xpd[ee_mode], 1, 4, 0, true))
-		return false;
+			ee->ee_xpd[ee_mode], 1, 4, 0, true))
+		return -EINVAL;
 
 	/* Write RF values */
 	for (i = 0; i < rf_size; i++) {
@@ -5284,14 +5279,14 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un
 		ath5k_hw_reg_write(hal, rf[i], rf5111_rf[i].rf_register);
 	}
 
-	return true;
+	return 0;
 }
 
 /*
  * Initialize RF5112
  */
-bool
-ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode)
+static int ath5k_hw_rf5112_rfregs(struct ath_hw *hal,
+		struct ieee80211_channel *channel, unsigned int mode)
 {
 	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
 	unsigned int rf_size;
@@ -5316,7 +5311,7 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un
 	for (i = 0; i < rf_size; i++) {
 		if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
 			AR5K_PRINT("invalid bank\n");
-			return false;
+			return -EINVAL;
 		}
 
 		if (bank != rf_ini[i].rf_bank) {
@@ -5336,12 +5331,12 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un
 		obdb = 0;
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-			ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
-			return false;
+				ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
+			return -EINVAL;
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-			ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
-			return false;
+				ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
+			return -EINVAL;
 	} else {
 		/* For 11a, Turbo and XR */
 		ee_mode = AR5K_EEPROM_MODE_11A;
@@ -5351,12 +5346,12 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un
 			    (channel->freq > 4000 ? 0 : -1)));
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-			ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
-			return false;
+				ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
+			return -EINVAL;
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-			ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
-			return false;
+				ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
+			return -EINVAL;
 	}
 
 #ifdef notyet
@@ -5367,19 +5362,19 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un
 #endif
 
 	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-		ee->ee_xpd[ee_mode], 1, 302, 0, true))
-		return false;
+			ee->ee_xpd[ee_mode], 1, 302, 0, true))
+		return -EINVAL;
 
 	/* Modify bank 7 */
 	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
-		ee->ee_i_gain[ee_mode], 6, 14, 0, true))
-		return false;
+			ee->ee_i_gain[ee_mode], 6, 14, 0, true))
+		return -EINVAL;
 
 	/* Write RF values */
 	for (i = 0; i < rf_size; i++)
 		ath5k_hw_reg_write(hal, rf[i], rf_ini[i].rf_register);
 
-	return true;
+	return 0;
 }
 
 /*
@@ -5387,9 +5382,9 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un
  * TODO: is this needed ? i mean 5211 has a 5111 RF
  * doesn't ar5k_rfregs work ?
  */
-void
-ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int freq,
-    unsigned int ee_mode)
+static void ath5k_hw_ar5211_rfregs(struct ath_hw *hal,
+		struct ieee80211_channel *channel, unsigned int freq,
+		unsigned int ee_mode)
 {
 	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
 	struct ath5k_ar5211_ini_rf rf[ARRAY_SIZE(ar5211_rf)];
@@ -5476,8 +5471,7 @@ ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq)
 	return true;
 }
 
-enum ath5k_rfgain
-ath5k_hw_get_rf_gain(struct ath_hw *hal)
+enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal)
 {
 	u32 data, type;
 
@@ -5502,18 +5496,18 @@ ath5k_hw_get_rf_gain(struct ath_hw *hal)
 		if (hal->ah_radio == AR5K_RF5112) {
 			ath5k_hw_rfregs_gainf_corr(hal);
 			hal->ah_gain.g_current =
-				hal->ah_gain.g_current >= hal->ah_gain.g_f_corr ?
-				(hal->ah_gain.g_current - hal->ah_gain.g_f_corr) :
+				hal->ah_gain.g_current>=hal->ah_gain.g_f_corr ?
+				(hal->ah_gain.g_current-hal->ah_gain.g_f_corr) :
 				0;
 		}
 
 		if (ath5k_hw_rfregs_gain_readback(hal) &&
-		AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) &&
-		ath5k_hw_rfregs_gain_adjust(hal))
+				AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) &&
+				ath5k_hw_rfregs_gain_adjust(hal))
 			hal->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE;
 	}
 
- done:
+done:
 	return hal->ah_rf_gain;
 }
 

commit 5a8f187a0243fb0cd52b4464e5b85aafe45c6b04
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Sun Jul 15 15:45:46 2007 +0200

    backport madwifi-old-openhal release 2539

diff --git a/ath5k_hw.c b/ath5k_hw.c
index a96053f..2b8cce7 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -69,12 +69,18 @@ static int ath5k_eeprom_read_mac(struct ath_hw *, u8 *);
 /*
  * Initial register dumps
  */
-static const struct ath5k_ar5212_ini ar5212_ini[] = AR5K_AR5212_INI;
-static const struct ath5k_ar5212_ini_mode ar5212_mode[] = AR5K_AR5212_INI_MODE;
+static const struct ath5k_ini ar5210_ini[] = AR5K_AR5210_INI;
 static const struct ath5k_ini ar5211_ini[] = AR5K_AR5211_INI;
+static const struct ath5k_ini ar5212_ini[] = AR5K_AR5212_INI;
 static const struct ath5k_ar5211_ini_mode ar5211_mode[] = AR5K_AR5211_INI_MODE;
+static const struct ath5k_ar5212_ini_mode ar5212_mode[] = AR5K_AR5212_INI_MODE;
+
+/* RF Initial BB gain settings */
+static const struct ath5k_ini rf5111_bbgain_ini[] = AR5K_RF5111_BBGAIN_INI;
+static const struct ath5k_ini rf5112_bbgain_ini[] = AR5K_RF5112_BBGAIN_INI;
+
+/* This is going out soon */
 static const struct ath5k_ar5211_ini_rf ar5211_rf[] = AR5K_AR5211_INI_RF;
-static const struct ath5k_ini ar5210_ini[] = AR5K_AR5210_INI;
 
 /*
  * Initial gain optimization values
@@ -83,11 +89,13 @@ static const struct ath5k_gain_opt rf5111_gain_opt = AR5K_RF5111_GAIN_OPT;
 static const struct ath5k_gain_opt rf5112_gain_opt = AR5K_RF5112_GAIN_OPT;
 
 /*
- * Initial register for the radio chipsets
+ * Initial register settings for the radio chipsets
  */
+/* RF Banks */
 static const struct ath5k_ini_rf rf5111_rf[] = AR5K_RF5111_INI_RF;
 static const struct ath5k_ini_rf rf5112_rf[] = AR5K_RF5112_INI_RF;
 static const struct ath5k_ini_rf rf5112a_rf[] = AR5K_RF5112A_INI_RF;
+/* Common (5111/5112) rf gain table */
 static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN;
 
 /*
@@ -252,7 +260,34 @@ static int ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag,
 	return (i <= 0) ? -EAGAIN : 0;
 }
 
+/*
+ * Write initial register dump
+ */
+static void ath5k_hw_ini_registers(struct ath_hw *hal, unsigned int size,
+		const struct ath5k_ini *ini_regs, bool change_channel)
+{
+	unsigned int i;
 
+	/* Write initial registers */
+	for (i = 0; i < size; i++) {
+		if (change_channel &&
+				ini_regs[i].ini_register >= AR5K_PCU_MIN &&
+				ini_regs[i].ini_register <= AR5K_PCU_MAX)
+			continue;
+
+		switch (ini_regs[i].ini_mode) {
+		case AR5K_INI_READ:
+			/* Cleared on read */
+			ath5k_hw_reg_read(hal, ini_regs[i].ini_register);
+			break;
+		case AR5K_INI_WRITE:
+		default:
+			AR5K_REG_WAIT(i);
+			ath5k_hw_reg_write(hal, ini_regs[i].ini_value,
+					ini_regs[i].ini_register);
+		}
+	}
+}
 
 /***************************************\
 	Attach/Detach Functions
@@ -490,7 +525,7 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial)
 		} else if (flags & CHANNEL_G) {
 			/* Dynamic OFDM/CCK is not supported by the AR5211 */
 			if (hal->ah_version == AR5K_AR5211) {
-				mode |= AR5K_PHY_MODE_MOD_OFDM;
+				mode |= AR5K_PHY_MODE_MOD_CCK;
 			} else {
 				mode |= AR5K_PHY_MODE_MOD_DYN;
 			}
@@ -831,61 +866,36 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 	}
 
 	/*
-	 * Write initial register settings
-	 * TODO:Do this in a common way
+	 * Initial register dump common for all modes
 	 */
 	/*For 5212*/
 	if (hal->ah_version == AR5K_AR5212) {
-		for (i = 0; i < ARRAY_SIZE(ar5212_ini); i++) {
-			if (change_channel == true &&
-			    ar5212_ini[i].ini_register >= AR5K_PCU_MIN &&
-			    ar5212_ini[i].ini_register <= AR5K_PCU_MAX)
-				continue;
-
-			if ((hal->ah_radio == AR5K_RF5111 &&
-			    ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5111) ||
-			    (hal->ah_radio == AR5K_RF5112 &&
-			    ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5112)) {
-				AR5K_REG_WAIT(i);
-				ath5k_hw_reg_write(hal,
-					ar5212_ini[i].ini_value,
-					(u32)ar5212_ini[i].ini_register);
-			}
-		}
-	}
-	/*For 5211*/
-	if (hal->ah_version == AR5K_AR5211) {
-		for (i = 0; i < ARRAY_SIZE(ar5211_ini); i++) {
-			if (change_channel == true &&
-			    ar5211_ini[i].ini_register >= AR5K_PCU_MIN &&
-			    ar5211_ini[i].ini_register <= AR5K_PCU_MAX)
-				continue;
-
-			AR5K_REG_WAIT(i);
-			ath5k_hw_reg_write(hal,
-				ar5211_ini[i].ini_value,
-				(u32)ar5211_ini[i].ini_register);
-		}
-	}
-	/*For 5210*/
-	if (hal->ah_version == AR5K_AR5210)
-		for (i = 0; i < ARRAY_SIZE(ar5210_ini); i++) {
-			if (change_channel == true &&
-			    ar5210_ini[i].ini_register >= AR5K_PCU_MIN &&
-			    ar5210_ini[i].ini_register <= AR5K_PCU_MAX)
-				continue;
-
-			switch (ar5210_ini[i].ini_mode) {
-				case AR5K_INI_READ:
-				/* Cleared on read */
-				ath5k_hw_reg_read(hal, ar5210_ini[i].ini_register);
-				break;
-
-			case AR5K_INI_WRITE:
-			default:
-				ath5k_hw_reg_write(hal, ar5210_ini[i].ini_value,
-					ar5210_ini[i].ini_register);
+		ath5k_hw_ini_registers(hal, ARRAY_SIZE(ar5212_ini),
+				ar5212_ini, change_channel);
+		if (hal->ah_radio == AR5K_RF5112) {
+			ath5k_hw_reg_write(hal, AR5K_PHY_PAPD_PROBE_INI_5112,
+					AR5K_PHY_PAPD_PROBE);
+			ath5k_hw_ini_registers(hal,
+					ARRAY_SIZE(rf5112_bbgain_ini),
+					rf5112_bbgain_ini, change_channel);
+		} else if (hal->ah_radio == AR5K_RF5111) {
+			ath5k_hw_reg_write(hal, AR5K_PHY_GAIN_2GHZ_INI_5111,
+					AR5K_PHY_GAIN_2GHZ);
+			ath5k_hw_reg_write(hal, AR5K_PHY_PAPD_PROBE_INI_5111,
+					AR5K_PHY_PAPD_PROBE);
+			ath5k_hw_ini_registers(hal,
+					ARRAY_SIZE(rf5111_bbgain_ini),
+					rf5111_bbgain_ini, change_channel);
 		}
+	} else if (hal->ah_version == AR5K_AR5211) {
+		ath5k_hw_ini_registers(hal, ARRAY_SIZE(ar5211_ini),
+				ar5211_ini, change_channel);
+		/* AR5211 only comes with 5111 */
+		ath5k_hw_ini_registers(hal, ARRAY_SIZE(rf5111_bbgain_ini),
+				rf5111_bbgain_ini, change_channel);
+	} else if (hal->ah_version == AR5K_AR5210) {
+		ath5k_hw_ini_registers(hal, ARRAY_SIZE(ar5210_ini),
+				ar5210_ini, change_channel);
 	}
 	
 	/*
@@ -3185,34 +3195,30 @@ int ath5k_hw_set_key(struct ath_hw *hal, u16 entry,
 		const struct ieee80211_key_conf *key, const u8 *mac)
 {
 	unsigned int i;
-	u32 key_v[AR5K_KEYCACHE_SIZE - 2] = {};
+	__le32 key_v[5] = {};
+	u32 keytype;
 
 	AR5K_TRACE;
 	AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
 
 	switch (key->keylen) {
 	case 40 / 8:
-		memcpy(&key_v[0], key->key, 4);
-		memcpy(&key_v[1], key->key + 4, 1);
-		key_v[5] = AR5K_KEYTABLE_TYPE_40;
+		memcpy(&key_v[0], key->key, 5);
+		keytype = AR5K_KEYTABLE_TYPE_40;
 		break;
 
 	case 104 / 8:
-		memcpy(&key_v[0], key->key, 4);
-		memcpy(&key_v[1], key->key + 4, 2);
-		memcpy(&key_v[2], key->key + 6, 4);
-		memcpy(&key_v[3], key->key + 10, 2);
-		memcpy(&key_v[4], key->key + 12, 1);
-		key_v[5] = AR5K_KEYTABLE_TYPE_104;
+		memcpy(&key_v[0], &key->key[0], 6);
+		memcpy(&key_v[2], &key->key[6], 6);
+		memcpy(&key_v[4], &key->key[12], 1);
+		keytype = AR5K_KEYTABLE_TYPE_104;
 		break;
 
 	case 128 / 8:
-		memcpy(&key_v[0], key->key, 4);
-		memcpy(&key_v[1], key->key + 4, 2);
-		memcpy(&key_v[2], key->key + 6, 4);
-		memcpy(&key_v[3], key->key + 10, 2);
-		memcpy(&key_v[4], key->key + 12, 4);
-		key_v[5] = AR5K_KEYTABLE_TYPE_128;
+		memcpy(&key_v[0], &key->key[0], 6);
+		memcpy(&key_v[2], &key->key[6], 6);
+		memcpy(&key_v[4], &key->key[12], 4);
+		keytype = AR5K_KEYTABLE_TYPE_128;
 		break;
 
 	default:
@@ -3220,7 +3226,10 @@ int ath5k_hw_set_key(struct ath_hw *hal, u16 entry,
 	}
 
 	for (i = 0; i < ARRAY_SIZE(key_v); i++)
-		ath5k_hw_reg_write(hal, key_v[i], AR5K_KEYTABLE_OFF(entry, i));
+		ath5k_hw_reg_write(hal, le32_to_cpu(key_v[i]),
+				AR5K_KEYTABLE_OFF(entry, i));
+
+	ath5k_hw_reg_write(hal, keytype, AR5K_KEYTABLE_TYPE(entry));
 
 	return ath5k_hw_set_key_lladdr(hal, entry, mac);
 }
@@ -4586,8 +4595,8 @@ ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
 	 * Set the channel and wait
 	 */
 	data = ath5k_hw_rf5110_chan2athchan(channel);
-	AR5K_PHY_WRITE(hal, 0x27, data);
-	AR5K_PHY_WRITE(hal, 0x30, 0);
+	ath5k_hw_reg_write(hal, data, AR5K_RF_BUFFER);
+	ath5k_hw_reg_write(hal, 0, AR5K_RF_BUFFER_CONTROL_0);
 	mdelay(1);
 
 	return true;
@@ -4660,8 +4669,10 @@ ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
 		    | (clock << 1) | (1 << 10) | 1;
 	}
 
-	AR5K_PHY_WRITE(hal, 0x27, (data1 & 0xff) | ((data0 & 0xff) << 8));
-	AR5K_PHY_WRITE(hal, 0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00));
+	ath5k_hw_reg_write(hal, (data1 & 0xff) | ((data0 & 0xff) << 8),
+			AR5K_RF_BUFFER);
+	ath5k_hw_reg_write(hal, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
+			AR5K_RF_BUFFER_CONTROL_3);
 
 	return true;
 }
@@ -4708,8 +4719,8 @@ ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
 
 	data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
 
-	AR5K_PHY_WRITE(hal, 0x27, data & 0xff);
-	AR5K_PHY_WRITE(hal, 0x36, (data >> 8) & 0x7f);
+	ath5k_hw_reg_write(hal, data & 0xff, AR5K_RF_BUFFER);
+	ath5k_hw_reg_write(hal, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
 
 	return true;
 }
@@ -5207,6 +5218,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un
 		rf[i] = rf5111_rf[i].rf_value[mode];
 	}
 
+	/* Modify bank 0 */
 	if (channel->val & CHANNEL_2GHZ) {
 		if (channel->val & CHANNEL_B)
 			ee_mode = AR5K_EEPROM_MODE_11B;
@@ -5223,6 +5235,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un
 			return false;
 
 		obdb = 1;
+	/* Modify bank 6 */
 	} else {
 		/* For 11a, Turbo and XR */
 		ee_mode = AR5K_EEPROM_MODE_11A;
@@ -5256,6 +5269,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un
 		obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
 		return false;
 
+	/* Modify bank 7 */
 	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
 		ee->ee_i_gain[ee_mode], 6, 29, 0, true))
 		return false;
@@ -5313,6 +5327,7 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un
 		rf[i] = rf_ini[i].rf_value[mode];
 	}
 
+	/* Modify bank 6 */
 	if (channel->val & CHANNEL_2GHZ) {
 		if (channel->val & CHANNEL_B)
 			ee_mode = AR5K_EEPROM_MODE_11B;
@@ -5355,6 +5370,7 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un
 		ee->ee_xpd[ee_mode], 1, 302, 0, true))
 		return false;
 
+	/* Modify bank 7 */
 	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
 		ee->ee_i_gain[ee_mode], 6, 14, 0, true))
 		return false;

commit f6fd65e1294437465f031aaae968dd7bd3cb3277
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Sun Jul 15 13:49:07 2007 +0200

    one (top) dir with all files

diff --git a/ath5k_hw.c b/ath5k_hw.c
new file mode 100644
index 0000000..a96053f
--- /dev/null
+++ b/ath5k_hw.c
@@ -0,0 +1,5825 @@
+ /*
+ * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
+ * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id$
+ */
+
+/*
+ * HAL interface for Atheros Wireless LAN devices.
+ * (Please have a look at ar5xxx.h for further information)
+ */
+
+#include <linux/pci.h>
+
+#include <asm/unaligned.h>
+#include <linux/pci.h>
+
+#include "ath5k.h"
+#include "ath5k_reg.h"
+
+/*Rate tables*/
+static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A;
+static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B;
+static const struct ath5k_rate_table ath5k_rt_11g = AR5K_RATES_11G;
+static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO;
+static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR;
+
+/*Prototypes*/
+static int ath5k_hw_nic_reset(struct ath_hw *, u32);
+static int ath5k_hw_nic_wakeup(struct ath_hw *, int, bool);
+static u16 ath5k_hw_radio_revision(struct ath_hw *, unsigned int);
+static int ath5k_hw_txpower(struct ath_hw *, struct ieee80211_channel *, unsigned int);
+static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *, struct ath_desc *,
+	unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
+	unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
+	unsigned int, unsigned int);
+static bool ath5k_hw_setup_xr_tx_desc(struct ath_hw *, struct ath_desc *,
+	unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
+	unsigned int);
+static int ath5k_hw_fill_4word_tx_desc(struct ath_hw *, struct ath_desc *,
+	unsigned int, bool, bool);
+static int ath5k_hw_proc_4word_tx_status(struct ath_hw *, struct ath_desc *);
+static int ath5k_hw_setup_2word_tx_desc(struct ath_hw *, struct ath_desc *,
+	unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
+	unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
+	unsigned int, unsigned int);
+static int ath5k_hw_fill_2word_tx_desc(struct ath_hw *, struct ath_desc *,
+	unsigned int, bool, bool);
+static int ath5k_hw_proc_2word_tx_status(struct ath_hw *, struct ath_desc *);
+static int ath5k_hw_proc_new_rx_status(struct ath_hw *, struct ath_desc *);
+static int ath5k_hw_proc_old_rx_status(struct ath_hw *, struct ath_desc *);
+static int ath5k_hw_get_capabilities(struct ath_hw *);
+
+static int ath5k_eeprom_init(struct ath_hw *);
+static int ath5k_eeprom_read_mac(struct ath_hw *, u8 *);
+
+/*
+ * Initial register dumps
+ */
+static const struct ath5k_ar5212_ini ar5212_ini[] = AR5K_AR5212_INI;
+static const struct ath5k_ar5212_ini_mode ar5212_mode[] = AR5K_AR5212_INI_MODE;
+static const struct ath5k_ini ar5211_ini[] = AR5K_AR5211_INI;
+static const struct ath5k_ar5211_ini_mode ar5211_mode[] = AR5K_AR5211_INI_MODE;
+static const struct ath5k_ar5211_ini_rf ar5211_rf[] = AR5K_AR5211_INI_RF;
+static const struct ath5k_ini ar5210_ini[] = AR5K_AR5210_INI;
+
+/*
+ * Initial gain optimization values
+ */
+static const struct ath5k_gain_opt rf5111_gain_opt = AR5K_RF5111_GAIN_OPT;
+static const struct ath5k_gain_opt rf5112_gain_opt = AR5K_RF5112_GAIN_OPT;
+
+/*
+ * Initial register for the radio chipsets
+ */
+static const struct ath5k_ini_rf rf5111_rf[] = AR5K_RF5111_INI_RF;
+static const struct ath5k_ini_rf rf5112_rf[] = AR5K_RF5112_INI_RF;
+static const struct ath5k_ini_rf rf5112a_rf[] = AR5K_RF5112A_INI_RF;
+static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN;
+
+/*
+ * Enable to overwrite the country code (use "00" for debug)
+ */
+#if 0
+#define COUNTRYCODE "00"
+#endif
+
+/*******************\
+  General Functions
+\*******************/
+
+
+/*
+ * Calculate transmition time of a frame
+ * TODO: Left here for combatibility, change it in ath5k
+ */
+u16 /*TODO: Is this really hardware dependent ?*/
+ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates,
+    u32 frame_length, u16 rate_index, bool short_preamble)
+{
+	const struct ath5k_rate *rate;
+	u32 value;
+
+	AR5K_ASSERT_ENTRY(rate_index, rates->rate_count);
+
+	/*
+	 * Get rate by index
+	 */
+	rate = &rates->rates[rate_index];
+
+	/*
+	 * Calculate the transmission time by operation (PHY) mode
+	 */
+	switch (rate->modulation) {
+	case MODULATION_CCK:
+		/*
+		 * CCK / DS mode (802.11b)
+		 */
+		value = AR5K_CCK_TX_TIME(rate->rate_kbps, frame_length,
+		    (short_preamble && (rate->modulation == MODULATION_CCK_SP)));
+		break;
+
+	case MODULATION_OFDM:
+		/*
+		 * Orthogonal Frequency Division Multiplexing
+		 */
+		if (AR5K_OFDM_NUM_BITS_PER_SYM(rate->rate_kbps) == 0)
+			return 0;
+		value = AR5K_OFDM_TX_TIME(rate->rate_kbps, frame_length);
+		break;
+
+	case MODULATION_TURBO:
+		/*
+		 * Orthogonal Frequency Division Multiplexing
+		 * Atheros "Turbo Mode" (doubled rates)
+		 */
+		if (AR5K_TURBO_NUM_BITS_PER_SYM(rate->rate_kbps) == 0)
+			return 0;
+		value = AR5K_TURBO_TX_TIME(rate->rate_kbps, frame_length);
+		break;
+
+	case MODULATION_XR:
+		/*
+		 * Orthogonal Frequency Division Multiplexing
+		 * Atheros "eXtended Range" (XR)
+		 */
+		if (AR5K_XR_NUM_BITS_PER_SYM(rate->rate_kbps) == 0)
+			return 0;
+		value = AR5K_XR_TX_TIME(rate->rate_kbps, frame_length);
+		break;
+
+	default:
+		return 0;
+	}
+
+	return value;
+}
+
+/*
+ * Functions used internaly
+ */
+
+static u32
+ath5k_hw_bitswap(u32 val, unsigned int bits)
+{
+	u32 retval = 0, bit, i;
+
+	for (i = 0; i < bits; i++) {
+		bit = (val >> i) & 1;
+		retval = (retval << 1) | bit;
+	}
+
+	return retval;
+}
+
+static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
+{
+	return turbo == true ? (usec * 80) : (usec * 40);
+}
+
+static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
+{
+	return turbo == true ? (clock / 80) : (clock / 40);
+}
+
+/*
+ * Read from a device register
+ */
+static inline u32 ath5k_hw_reg_read(struct ath_hw *hal, u16 reg)
+{
+	return readl(hal->ah_sh + reg);
+}
+
+/*
+ * Write to a device register
+ */
+static inline void ath5k_hw_reg_write(struct ath_hw *hal, u32 val, u16 reg)
+{
+	writel(val, hal->ah_sh + reg);
+}
+
+static inline __u16 ath5k_hw_unaligned_read_16(__le16 *p)
+{
+	return le16_to_cpu(get_unaligned(p));
+}
+
+static inline void ath5k_hw_unaligned_write_16(__u16 v, __le16* p)
+{
+	put_unaligned(cpu_to_le16(v), p);
+}
+
+static inline __u32 ath5k_hw_unaligned_read_32(__le32 *p)
+{
+	return le32_to_cpu(get_unaligned(p));
+}
+
+static inline void ath5k_hw_unaligned_write_32(__u32 v, __le32 *p)
+{
+	put_unaligned(cpu_to_le32(v), p);
+}
+
+/*
+ * Check if a register write has been completed
+ */
+static int ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag,
+		u32 val, bool is_set)
+{
+	int i;
+	u32 data;
+
+	for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
+		data = ath5k_hw_reg_read(hal, reg);
+		if ((is_set == true) && (data & flag))
+			break;
+		else if ((data & flag) == val)
+			break;
+		udelay(15);
+	}
+
+	return (i <= 0) ? -EAGAIN : 0;
+}
+
+
+
+/***************************************\
+	Attach/Detach Functions
+\***************************************/
+
+/*
+ * Check if the device is supported and initialize the needed structs
+ */
+struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc,
+		void __iomem *sh)
+{
+	struct ath_hw *hal;
+	u8 mac[ETH_ALEN];
+	int ret;
+	u32 srev;
+
+	/*TODO:Use eeprom_magic to verify chipset*/
+
+	/*If we passed the test malloc a hal struct*/
+	hal = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
+	if (hal == NULL) {
+		ret = -ENOMEM;
+		AR5K_PRINT("out of memory\n");
+		goto err;
+	}
+
+	hal->ah_sc = sc;
+	hal->ah_sh = sh;
+
+	/*
+	 * HAL information
+	 */
+
+	/* Regulation Stuff */
+	hal->ah_country_code = AR5K_TUNE_CTRY;
+	ath5k_get_regdomain(hal);
+
+	hal->ah_op_mode = IEEE80211_IF_TYPE_STA;
+	hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
+	hal->ah_turbo = false;
+	hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
+	hal->ah_imr = 0;
+	hal->ah_atim_window = 0;
+	hal->ah_aifs = AR5K_TUNE_AIFS;
+	hal->ah_cw_min = AR5K_TUNE_CWMIN;
+	hal->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
+	hal->ah_software_retry = false;
+	hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
+
+	switch (device) {
+		case PCI_DEVICE_ID_ATHEROS_AR2413:
+		case PCI_DEVICE_ID_ATHEROS_AR5413:
+		case PCI_DEVICE_ID_ATHEROS_AR5424:
+			/*
+			 * Known single chip solutions
+			 */
+			hal->ah_single_chip = true;
+			break;
+		default:
+			/*
+			 * Multi chip solutions
+			 */
+			hal->ah_single_chip = false;
+			break;
+	}
+
+	/*
+	 * Set the mac revision based on the pci id
+	 */
+	hal->ah_version	= mac_version;
+
+	/*Fill the hal struct with the needed functions*/
+	if (hal->ah_version == AR5K_AR5212)
+		hal->ah_magic = AR5K_EEPROM_MAGIC_5212;
+	else if (hal->ah_version == AR5K_AR5211)
+		hal->ah_magic = AR5K_EEPROM_MAGIC_5211;
+
+	if (hal->ah_version == AR5K_AR5212) {
+		hal->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
+		hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
+		hal->ah_fill_tx_desc = ath5k_hw_fill_4word_tx_desc;
+		hal->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
+	} else {
+		hal->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
+		hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
+		hal->ah_fill_tx_desc = ath5k_hw_fill_2word_tx_desc;
+		hal->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
+	}
+
+	if (hal->ah_version == AR5K_AR5212)
+		hal->ah_proc_rx_desc = ath5k_hw_proc_new_rx_status;
+	else if (hal->ah_version <= AR5K_AR5211)
+		hal->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status;
+
+	/* Bring device out of sleep and reset it's units */
+	ret = ath5k_hw_nic_wakeup(hal, AR5K_INIT_MODE, true);
+	if (ret)
+		goto err_free;
+
+	/* Get MAC, PHY and RADIO revisions */
+	srev = ath5k_hw_reg_read(hal, AR5K_SREV);
+	hal->ah_mac_srev = srev;
+	hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
+	hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
+	hal->ah_phy_revision = ath5k_hw_reg_read(hal, AR5K_PHY_CHIP_ID) & 0x00ffffffff;
+	hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal,CHANNEL_5GHZ);
+
+	if (hal->ah_version == AR5K_AR5210) {
+		hal->ah_radio_2ghz_revision = 0;
+	} else {
+		hal->ah_radio_2ghz_revision = ath5k_hw_radio_revision(hal,
+				CHANNEL_2GHZ);
+	}
+
+	/* Single chip radio */
+	if (hal->ah_radio_2ghz_revision == hal->ah_radio_5ghz_revision)
+		hal->ah_radio_2ghz_revision = 0;
+
+	/* Identify the radio chip*/
+	if (hal->ah_version == AR5K_AR5210)
+		hal->ah_radio = AR5K_RF5110;
+	else
+		hal->ah_radio = hal->ah_radio_5ghz_revision <
+			AR5K_SREV_RAD_5112 ? AR5K_RF5111 : AR5K_RF5112;
+
+	hal->ah_phy = AR5K_PHY(0);
+
+	/* Set MAC to bcast: ff:ff:ff:ff:ff:ff, this is using 'mac' as a 
+ 	 * temporary variable for setting our BSSID. Right bellow we update 
+ 	 * it with ath5k_hw_get_lladdr() */
+	memset(mac, 0xff, ETH_ALEN);
+	ath5k_hw_set_associd(hal, mac, 0);
+
+	ath5k_hw_get_lladdr(hal, mac);
+	ath5k_hw_set_opmode(hal);
+		
+#ifdef AR5K_DEBUG
+	hal->ah_dump_state(hal);
+#endif
+
+	/*
+	 * Get card capabilities, values, ...
+	 */
+
+	ret = ath5k_eeprom_init(hal);
+	if (ret) {
+		AR5K_PRINT("unable to init EEPROM\n");
+		goto err_free;
+	}
+
+	/* Get misc capabilities */
+	ret = ath5k_hw_get_capabilities(hal);
+	if (ret) {
+		AR5K_PRINTF("unable to get device capabilities: 0x%04x\n",
+			device);
+		goto err_free;
+	}
+
+	/* Get MAC address */
+	ret = ath5k_eeprom_read_mac(hal, mac);
+	if (ret) {
+		AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n",
+			device);
+		goto err_free;
+	}
+
+	ath5k_hw_set_lladdr(hal, mac);
+
+	/* Initialize the gain optimization values */
+	/*For RF5111*/
+	if (hal->ah_radio == AR5K_RF5111) {
+		hal->ah_gain.g_step_idx = rf5111_gain_opt.go_default;
+		hal->ah_gain.g_step =
+		    &rf5111_gain_opt.go_step[hal->ah_gain.g_step_idx];
+		hal->ah_gain.g_low = 20;
+		hal->ah_gain.g_high = 35;
+		hal->ah_gain.g_active = 1;
+	/*For RF5112*/
+	} else if (hal->ah_radio == AR5K_RF5112) {
+		hal->ah_gain.g_step_idx = rf5112_gain_opt.go_default;
+		hal->ah_gain.g_step =
+		    &rf5111_gain_opt.go_step[hal->ah_gain.g_step_idx];
+		hal->ah_gain.g_low = 20;
+		hal->ah_gain.g_high = 85;
+		hal->ah_gain.g_active = 1;
+	}
+
+	return hal;
+err_free:
+	kfree(hal);
+err:
+	return ERR_PTR(ret);
+}
+
+/*
+ * Bring up MAC + PHY Chips
+ */
+static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial)
+{
+	u32 turbo, mode, clock;
+	int ret;
+
+	turbo = 0;
+	mode = 0;
+	clock = 0;
+
+	AR5K_TRACE;
+
+	if (hal->ah_version != AR5K_AR5210) {
+		/*
+		 * Get channel mode flags
+		 */
+ 
+		if (hal->ah_radio >= AR5K_RF5112) {
+			mode = AR5K_PHY_MODE_RAD_RF5112;
+			clock = AR5K_PHY_PLL_RF5112;
+		} else {
+			mode = AR5K_PHY_MODE_RAD_RF5111;	/*Zero*/
+			clock = AR5K_PHY_PLL_RF5111;		/*Zero*/
+		}
+
+		if (flags & CHANNEL_2GHZ) {
+			mode |= AR5K_PHY_MODE_FREQ_2GHZ;
+			clock |= AR5K_PHY_PLL_44MHZ;
+		} else if (flags & CHANNEL_5GHZ) {
+			mode |= AR5K_PHY_MODE_FREQ_5GHZ;
+			clock |= AR5K_PHY_PLL_40MHZ;
+		} else {
+			AR5K_PRINT("invalid radio frequency mode\n");
+			return -EINVAL;
+		}
+
+		if (flags & CHANNEL_CCK) {
+			mode |= AR5K_PHY_MODE_MOD_CCK;
+		} else if (flags & CHANNEL_G) {
+			/* Dynamic OFDM/CCK is not supported by the AR5211 */
+			if (hal->ah_version == AR5K_AR5211) {
+				mode |= AR5K_PHY_MODE_MOD_OFDM;
+			} else {
+				mode |= AR5K_PHY_MODE_MOD_DYN;
+			}
+		} else if (flags & CHANNEL_OFDM) {
+			mode |= AR5K_PHY_MODE_MOD_OFDM;
+		} else {
+			AR5K_PRINT("invalid radio frequency mode\n");
+			return -EINVAL;
+		}
+
+		if (flags & CHANNEL_TURBO) {
+			turbo = AR5K_PHY_TURBO_MODE |
+			    AR5K_PHY_TURBO_SHORT;
+		}
+	}
+
+	/*
+	 * Reset and wakeup the device
+	 */
+
+	else {
+		if (initial == true) {
+			/* ...reset hardware */
+			if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_PCI)) {
+				AR5K_PRINT("failed to reset the PCI chipset\n");
+				return -EIO;
+			}
+
+			mdelay(1);
+		}
+
+		/* ...wakeup */
+		ret = ath5k_hw_set_power(hal, AR5K_PM_AWAKE, true, 0);
+		if (ret) {
+			AR5K_PRINT("failed to resume the MAC Chip\n");
+			return ret;
+		}
+
+		/* ...enable Atheros turbo mode if requested */
+		if (flags & CHANNEL_TURBO)
+			ath5k_hw_reg_write(hal, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO);
+
+		/* ...reset chipset */
+		if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP)) {
+			AR5K_PRINT("failed to reset the AR5210 chipset\n");
+			return -EIO;
+		}
+
+		mdelay(1);
+	}
+
+	/* ...reset chipset and PCI device */
+	if (hal->ah_single_chip == false && ath5k_hw_nic_reset(hal,
+				AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI)) {
+		AR5K_PRINT("failed to reset the MAC Chip + PCI\n");
+		return -EIO;
+	}
+
+	if (hal->ah_version == AR5K_AR5210)
+		udelay(2300);
+
+	/* ...wakeup */
+	ret = ath5k_hw_set_power(hal, AR5K_PM_AWAKE, true, 0);
+	if (ret) {
+		AR5K_PRINT("failed to resume the MAC Chip\n");
+		return ret;
+	}
+
+	/* ...final warm reset */
+	if (ath5k_hw_nic_reset(hal, 0)) {
+		AR5K_PRINT("failed to warm reset the MAC Chip\n");
+		return -EIO;
+	}
+
+	if (hal->ah_version != AR5K_AR5210){
+		/* ...set the PHY operating mode */
+		ath5k_hw_reg_write(hal, clock, AR5K_PHY_PLL);
+		udelay(300);
+
+		ath5k_hw_reg_write(hal, mode, AR5K_PHY_MODE);
+		ath5k_hw_reg_write(hal, turbo, AR5K_PHY_TURBO);
+	}
+
+	return 0;
+}
+
+/*
+ * Get the PHY Chip revision
+ */
+static u16
+ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan)
+{
+	int i;
+	u32 srev;
+	u16 ret;
+
+	AR5K_TRACE;
+
+	/*
+	 * Set the radio chip access register
+	 */
+	switch (chan) {
+	case CHANNEL_2GHZ:
+		ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
+		break;
+	case CHANNEL_5GHZ:
+		ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
+		break;
+	default:
+		return 0;
+	}
+
+	mdelay(2);
+
+	/* ...wait until PHY is ready and read the selected radio revision */
+	ath5k_hw_reg_write(hal, 0x00001c16, AR5K_PHY(0x34));
+
+	for (i = 0; i < 8; i++)
+		ath5k_hw_reg_write(hal, 0x00010000, AR5K_PHY(0x20));
+
+	if (hal->ah_version == AR5K_AR5210) {
+		srev = ath5k_hw_reg_read(hal, AR5K_PHY(256) >> 28) & 0xf;
+
+		ret = (u16) ath5k_hw_bitswap(srev, 4) + 1;
+	} else {
+		srev = (ath5k_hw_reg_read(hal, AR5K_PHY(0x100)) >> 24) & 0xff;
+
+		ret = (u16) ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8);
+	}
+
+	/* Reset to the 5GHz mode */
+	ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
+
+	return ret;
+}
+
+/*
+ * Get the rate table for a specific operation mode
+ * TODO:Limit this per chipset
+ */
+const struct ath5k_rate_table *
+ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode)
+{
+	AR5K_TRACE;
+
+	/* Get rate tables */
+	if (!test_bit(mode, hal->ah_capabilities.cap_mode))
+		return NULL;
+
+	switch (mode) {
+	case MODE_IEEE80211A:
+		return &ath5k_rt_11a;
+	case MODE_ATHEROS_TURBO:
+		return &ath5k_rt_turbo;
+	case MODE_IEEE80211B:
+		return &ath5k_rt_11b;
+	case MODE_IEEE80211G:
+		return &ath5k_rt_11g;
+	case MODE_ATHEROS_TURBOG:
+		return &ath5k_rt_xr;
+	default:
+		return NULL;
+	}
+
+	return NULL;
+}
+
+/*
+ * Free the hal struct
+ */
+void ath5k_hw_detach(struct ath_hw *hal)
+{
+	AR5K_TRACE;
+
+	if (hal->ah_rf_banks != NULL)
+		kfree(hal->ah_rf_banks);
+
+	/* assume interrupts are down */
+	kfree(hal);
+}
+
+/*******************************\
+	Reset Functions
+\*******************************/
+
+/*
+ * Main reset function
+ */
+int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
+	struct ieee80211_channel *channel, bool change_channel)
+{
+	const struct ath5k_rate_table *rt;
+	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
+	u32 data, noise_floor, s_seq, s_ant, s_led[3];
+	u8 mac[ETH_ALEN];
+	unsigned int i, phy, mode, freq, off, ee_mode, ant[2];
+	int ret;
+
+	AR5K_TRACE;
+
+	s_seq = 0;
+	s_ant = 1;
+	ee_mode = 0;
+	freq = 0;
+	mode = 0;
+	phy = 0;
+
+	/*
+	 * Save some registers before a reset
+	 */
+	/*DCU/Antenna selection not available on 5210*/
+	if (hal->ah_version != AR5K_AR5210) {
+		if (change_channel == true) {
+			/*Sequence number for queue 0 -do this for all queues ?*/
+			s_seq = ath5k_hw_reg_read(hal, AR5K_QUEUE_DFS_SEQNUM(0));
+			/*Default antenna*/
+			s_ant = ath5k_hw_reg_read(hal, AR5K_DEFAULT_ANTENNA);
+		}
+	}
+
+	/*GPIOs*/
+	s_led[0] = ath5k_hw_reg_read(hal, AR5K_PCICFG) &	AR5K_PCICFG_LEDSTATE;
+	s_led[1] = ath5k_hw_reg_read(hal, AR5K_GPIOCR);
+	s_led[2] = ath5k_hw_reg_read(hal, AR5K_GPIODO);
+
+	if (change_channel == true && hal->ah_rf_banks != NULL)
+		ath5k_hw_get_rf_gain(hal);
+
+
+	/*Wakeup the device*/
+	ret = ath5k_hw_nic_wakeup(hal, channel->val, false);
+	if (ret)
+		return ret;
+
+	/*
+	 * Initialize operating mode
+	 */
+	hal->ah_op_mode = op_mode;
+
+	/*
+	 * 5111/5112 Settings
+	 * 5210 only comes with RF5110
+	 */
+	if (hal->ah_version != AR5K_AR5210) {
+		if (hal->ah_radio == AR5K_RF5111)
+			phy = AR5K_INI_PHY_5111;
+		else if (hal->ah_radio == AR5K_RF5112)
+			phy = AR5K_INI_PHY_5112;
+		else {
+			AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio);
+			return -EINVAL;
+		}
+
+		switch (channel->val & CHANNEL_MODES) {
+		case CHANNEL_A:
+			mode = AR5K_INI_VAL_11A;
+			freq = AR5K_INI_RFGAIN_5GHZ;
+			ee_mode = AR5K_EEPROM_MODE_11A;
+			break;
+		case CHANNEL_B:
+			mode = AR5K_INI_VAL_11B;
+			freq = AR5K_INI_RFGAIN_2GHZ;
+			ee_mode = AR5K_EEPROM_MODE_11B;
+			break;
+		case CHANNEL_G:
+			mode = AR5K_INI_VAL_11G;
+			freq = AR5K_INI_RFGAIN_2GHZ;
+			ee_mode = AR5K_EEPROM_MODE_11G;
+			break;
+		case CHANNEL_T:
+			mode = AR5K_INI_VAL_11A_TURBO;
+			freq = AR5K_INI_RFGAIN_5GHZ;
+			ee_mode = AR5K_EEPROM_MODE_11A;
+			break;
+		/*Is this ok on 5211 too ?*/
+		case CHANNEL_TG:
+			mode = AR5K_INI_VAL_11G_TURBO;
+			freq = AR5K_INI_RFGAIN_2GHZ;
+			ee_mode = AR5K_EEPROM_MODE_11G;
+			break;
+		case CHANNEL_XR:
+			if (hal->ah_version == AR5K_AR5211) {
+				AR5K_PRINTF("XR mode not available on 5211");
+				return -EINVAL;
+			}
+			mode = AR5K_INI_VAL_XR;
+			freq = AR5K_INI_RFGAIN_5GHZ;
+			ee_mode = AR5K_EEPROM_MODE_11A;
+			break;
+		default:
+			AR5K_PRINTF("invalid channel: %d\n", channel->freq);
+			return -EINVAL;
+		}
+
+		/* PHY access enable */
+		ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
+
+		/*
+		 * Write initial RF registers on 5211
+		 * do we need that ? Is ath5k_hw_rfregs going to work for 5211 (5111) ?
+		 */
+		if (hal->ah_version == AR5K_AR5211)
+			ath5k_hw_ar5211_rfregs(hal, channel, freq, ee_mode);
+	}
+
+	/*
+	 * Write initial mode settings
+	 * TODO:Do this in a common way
+	 */
+	/*For 5212*/
+	if (hal->ah_version == AR5K_AR5212) {
+		for (i = 0; i < ARRAY_SIZE(ar5212_mode); i++) {
+			if (ar5212_mode[i].mode_flags == AR5K_INI_FLAG_511X)
+				off = AR5K_INI_PHY_511X;
+			else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5111 &&
+			    hal->ah_radio == AR5K_RF5111)
+				off = AR5K_INI_PHY_5111;
+			else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5112 &&
+			    hal->ah_radio == AR5K_RF5112)
+				off = AR5K_INI_PHY_5112;
+			else
+				continue;
+
+			AR5K_REG_WAIT(i);
+			ath5k_hw_reg_write(hal,
+					ar5212_mode[i].mode_value[off][mode],
+					(u32)ar5212_mode[i].mode_register);
+		}
+	}
+	/*For 5211*/
+	if (hal->ah_version == AR5K_AR5211) {
+		for (i = 0; i < ARRAY_SIZE(ar5211_mode); i++) {
+			AR5K_REG_WAIT(i);
+			ath5k_hw_reg_write(hal,
+				ar5211_mode[i].mode_value[mode],
+				(u32)ar5211_mode[i].mode_register);
+		}
+	}
+
+	/*
+	 * Write initial register settings
+	 * TODO:Do this in a common way
+	 */
+	/*For 5212*/
+	if (hal->ah_version == AR5K_AR5212) {
+		for (i = 0; i < ARRAY_SIZE(ar5212_ini); i++) {
+			if (change_channel == true &&
+			    ar5212_ini[i].ini_register >= AR5K_PCU_MIN &&
+			    ar5212_ini[i].ini_register <= AR5K_PCU_MAX)
+				continue;
+
+			if ((hal->ah_radio == AR5K_RF5111 &&
+			    ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5111) ||
+			    (hal->ah_radio == AR5K_RF5112 &&
+			    ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5112)) {
+				AR5K_REG_WAIT(i);
+				ath5k_hw_reg_write(hal,
+					ar5212_ini[i].ini_value,
+					(u32)ar5212_ini[i].ini_register);
+			}
+		}
+	}
+	/*For 5211*/
+	if (hal->ah_version == AR5K_AR5211) {
+		for (i = 0; i < ARRAY_SIZE(ar5211_ini); i++) {
+			if (change_channel == true &&
+			    ar5211_ini[i].ini_register >= AR5K_PCU_MIN &&
+			    ar5211_ini[i].ini_register <= AR5K_PCU_MAX)
+				continue;
+
+			AR5K_REG_WAIT(i);
+			ath5k_hw_reg_write(hal,
+				ar5211_ini[i].ini_value,
+				(u32)ar5211_ini[i].ini_register);
+		}
+	}
+	/*For 5210*/
+	if (hal->ah_version == AR5K_AR5210)
+		for (i = 0; i < ARRAY_SIZE(ar5210_ini); i++) {
+			if (change_channel == true &&
+			    ar5210_ini[i].ini_register >= AR5K_PCU_MIN &&
+			    ar5210_ini[i].ini_register <= AR5K_PCU_MAX)
+				continue;
+
+			switch (ar5210_ini[i].ini_mode) {
+				case AR5K_INI_READ:
+				/* Cleared on read */
+				ath5k_hw_reg_read(hal, ar5210_ini[i].ini_register);
+				break;
+
+			case AR5K_INI_WRITE:
+			default:
+				ath5k_hw_reg_write(hal, ar5210_ini[i].ini_value,
+					ar5210_ini[i].ini_register);
+		}
+	}
+	
+	/*
+	 * 5211/5212 Specific
+	 */
+	if (hal->ah_version != AR5K_AR5210) {
+		/*
+		 * Write initial RF gain settings
+		 * This should work for both 5111/5112
+		 */
+		if (ath5k_hw_rfgain(hal, phy, freq) == false) {
+			return -EIO;
+		}
+
+		mdelay(1);
+
+		/*
+		 * Set rate duration table on 5212
+		 */
+		if (hal->ah_version == AR5K_AR5212) {
+
+			/*For 802.11b*/
+			if (!(channel->val & CHANNEL_B)) {
+
+				/*Get rate table for this operation mode*/
+				rt = ath5k_hw_get_rate_table(hal,
+						MODE_IEEE80211B);
+
+				/*Write rate duration table*/
+				for (i = 0; i < rt->rate_count; i++) {
+					data = AR5K_RATE_DUR(rt->rates[i].rate_code);
+					ath5k_hw_reg_write(hal,
+						ath_hal_computetxtime(hal, rt,
+						14, rt->rates[i].control_rate,
+						false), data);
+					if (HAS_SHPREAMBLE(i)) {
+						ath5k_hw_reg_write(hal,
+						    ath_hal_computetxtime(hal, rt, 14,
+						    rt->rates[i].control_rate, false),
+						    data +
+						    (AR5K_SET_SHORT_PREAMBLE << 2));
+					}
+				}
+	
+			} else {
+			/*For 802.11a/g Turbo/XR mode (AR5K_MODE_XR here is O.K. for both a/g - OFDM)*/
+
+				/*Get rate table for this operation mode*/
+				rt = ath5k_hw_get_rate_table(hal,
+				    channel->val & CHANNEL_TURBO ?
+				    MODE_ATHEROS_TURBO : MODE_ATHEROS_TURBOG);
+
+				/*Write rate duration table*/
+				for (i = 0; i < rt->rate_count; i++) {
+					ath5k_hw_reg_write(hal,
+						ath_hal_computetxtime(hal, rt,
+						14, rt->rates[i].control_rate,
+						false),
+						AR5K_RATE_DUR(rt->rates[i].rate_code));
+				}
+
+			}
+		}
+
+		/* Fix for first revision of the RF5112 RF chipset */
+		if (hal->ah_radio >= AR5K_RF5112 && hal->ah_radio_5ghz_revision<
+				AR5K_SREV_RAD_5112A) {
+			ath5k_hw_reg_write(hal, AR5K_PHY_CCKTXCTL_WORLD,
+					AR5K_PHY_CCKTXCTL);
+			if (channel->val & CHANNEL_A)
+				data = 0xffb81020;
+			else
+				data = 0xffb80d20;
+			ath5k_hw_reg_write(hal, data, AR5K_PHY_FRAME_CTL);
+		}
+
+		/*
+		 * Set TX power (XXX use txpower from net80211)
+		 */
+		ret = ath5k_hw_txpower(hal, channel, AR5K_TUNE_DEFAULT_TXPOWER);
+		if (ret)
+			return ret;
+
+		/*
+		 * Write RF registers
+		 * TODO:Does this work on 5211 (5111) ?
+		 */
+		if (ath5k_hw_rfregs(hal, channel, mode) == false) {
+			return -EINPROGRESS;
+		}
+
+		/*
+		 * Configure additional registers
+		 */
+
+		/* Write OFDM timings on 5212*/
+		if (hal->ah_version == AR5K_AR5212) {
+			if (channel->val & CHANNEL_OFDM) {
+				u32 coef_scaled, coef_exp, coef_man, ds_coef_exp,
+				    ds_coef_man, clock;
+
+				clock = channel->val & CHANNEL_T ? 80 : 40;
+				coef_scaled = ((5 * (clock << 24)) / 2) / channel->freq;
+
+				for (coef_exp = 31; coef_exp > 0; coef_exp--)
+					if ((coef_scaled >> coef_exp) & 0x1)
+						break;
+
+				if (!coef_exp) {
+					return -EINVAL;
+				}
+
+				coef_exp = 14 - (coef_exp - 24);
+				coef_man = coef_scaled + (1 << (24 - coef_exp - 1));
+				ds_coef_man = coef_man >> (24 - coef_exp);
+				ds_coef_exp = coef_exp - 16;
+
+				AR5K_REG_WRITE_BITS(hal, AR5K_PHY_TIMING_3,
+				    AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
+				AR5K_REG_WRITE_BITS(hal, AR5K_PHY_TIMING_3,
+				    AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
+			}
+		}
+
+		/*Enable/disable 802.11b mode on 5111
+		(enable 2111 frequency converter + CCK)*/
+		if (hal->ah_radio == AR5K_RF5111) {
+			if (channel->val & CHANNEL_B)
+				AR5K_REG_ENABLE_BITS(hal, AR5K_TXCFG,
+				    AR5K_TXCFG_B_MODE);
+			else
+				AR5K_REG_DISABLE_BITS(hal, AR5K_TXCFG,
+				    AR5K_TXCFG_B_MODE);
+		}
+
+		/* Set antenna mode */
+		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x44),
+		    hal->ah_antenna[ee_mode][0], 0xfffffc06);
+
+			if (freq == AR5K_INI_RFGAIN_2GHZ)
+				ant[0] = ant[1] = AR5K_ANT_FIXED_B;
+			else
+				ant[0] = ant[1] = AR5K_ANT_FIXED_A;
+
+
+		ath5k_hw_reg_write(hal, hal->ah_antenna[ee_mode][ant[0]],
+			AR5K_PHY_ANT_SWITCH_TABLE_0);
+		ath5k_hw_reg_write(hal, hal->ah_antenna[ee_mode][ant[1]],
+			AR5K_PHY_ANT_SWITCH_TABLE_1);
+
+		/* Commit values from EEPROM */
+		if (hal->ah_radio == AR5K_RF5111)
+			AR5K_REG_WRITE_BITS(hal, AR5K_PHY_FRAME_CTL,
+			    AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip);
+
+		ath5k_hw_reg_write(hal,
+			AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
+			AR5K_PHY(0x5a));
+
+		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x11),
+		    (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f);
+		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x12),
+		    (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff);
+		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x14),
+		    (ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
+		    ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000);
+
+		ath5k_hw_reg_write(hal,
+			(ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
+			(ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
+			(ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
+			(ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d));
+
+		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x0a),
+		    ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
+		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x19),
+		    (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
+		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x49), 4, 0xffffff01);
+
+		AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ,
+		    AR5K_PHY_IQ_CORR_ENABLE |
+		    (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
+		    ee->ee_q_cal[ee_mode]);
+
+		if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
+			AR5K_REG_WRITE_BITS(hal, AR5K_PHY_GAIN_2GHZ,
+			    AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
+			    ee->ee_margin_tx_rx[ee_mode]);
+		}
+
+	} else {
+		mdelay(1);
+		/* Disable phy and wait */
+		ath5k_hw_reg_write(hal, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
+		mdelay(1);
+	}
+
+	/*
+	 * Restore saved values
+	 */
+	/*DCU/Antenna selection not available on 5210*/
+	if (hal->ah_version != AR5K_AR5210) {
+		ath5k_hw_reg_write(hal, s_seq, AR5K_QUEUE_DFS_SEQNUM(0));
+		ath5k_hw_reg_write(hal, s_ant, AR5K_DEFAULT_ANTENNA);
+	}
+	AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, s_led[0]);
+	ath5k_hw_reg_write(hal, s_led[1], AR5K_GPIOCR);
+	ath5k_hw_reg_write(hal, s_led[2], AR5K_GPIODO);
+
+	/*
+	 * Misc
+	 */
+	memset(mac, 0xff, ETH_ALEN);
+	ath5k_hw_set_associd(hal, mac, 0);
+	ath5k_hw_set_opmode(hal);
+	/*PISR/SISR Not available on 5210*/
+	if (hal->ah_version != AR5K_AR5210) {
+		ath5k_hw_reg_write(hal, 0xffffffff, AR5K_PISR);
+		/* XXX: AR5K_RSSI_THR has masks and shifts defined for it, so 
+ 		 * direct write using ath5k_hw_reg_write seems wrong. Test with:
+		 * AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR,
+		 *   AR5K_RSSI_THR_BMISS, AR5K_TUNE_RSSI_THRES);
+		 * with different variables and check results compared
+		 * to ath5k_hw_reg_write(hal, )  */
+		ath5k_hw_reg_write(hal, AR5K_TUNE_RSSI_THRES, AR5K_RSSI_THR);
+	}
+
+	/*
+	 * Set Rx/Tx DMA Configuration
+	 *(passing dma size not available on 5210)
+	 */
+	if (hal->ah_version != AR5K_AR5210) {
+		AR5K_REG_WRITE_BITS(hal, AR5K_TXCFG, AR5K_TXCFG_SDMAMR,
+				AR5K_DMASIZE_512B | AR5K_TXCFG_DMASIZE);
+		AR5K_REG_WRITE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_SDMAMW,
+				AR5K_DMASIZE_512B);
+	}
+
+	/*
+	 * Set channel and calibrate the PHY
+	 */
+	if (ath5k_hw_channel(hal, channel) == false)
+		return -EIO;
+
+	/*
+	 * Enable the PHY and wait until completion
+	 */
+	ath5k_hw_reg_write(hal, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
+
+	/*
+	 * 5111/5112 Specific
+	 */
+	if (hal->ah_version != AR5K_AR5210) {
+		data = ath5k_hw_reg_read(hal, AR5K_PHY_RX_DELAY) & AR5K_PHY_RX_DELAY_M;
+		data = (channel->val & CHANNEL_CCK) ?
+		    ((data << 2) / 22) : (data / 10);
+
+		udelay(100 + data);
+	} else {
+		mdelay(1);
+	}
+
+	/*
+	 * Enable calibration and wait until completion
+	 */
+	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL,
+				AR5K_PHY_AGCCTL_CAL);
+
+	if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
+			AR5K_PHY_AGCCTL_CAL, 0, false)) {
+		AR5K_PRINTF("calibration timeout (%uMHz)\n",
+		    channel->freq);
+		return -EAGAIN;
+	}
+
+	/*
+ 	 * Enable noise floor calibration and wait until completion
+ 	 */
+	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL,
+				AR5K_PHY_AGCCTL_NF);
+
+	if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
+			AR5K_PHY_AGCCTL_NF, 0, false)) {
+		AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n",
+				channel->freq);
+		return -EAGAIN;
+	}
+
+	/* Wait until the noise floor is calibrated and read the value */
+	for (i = 20; i > 0; i--) {
+		mdelay(1);
+		noise_floor = ath5k_hw_reg_read(hal, AR5K_PHY_NF);
+
+		if (AR5K_PHY_NF_RVAL(noise_floor) &
+		AR5K_PHY_NF_ACTIVE)
+			noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
+	
+		if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
+			break;
+	}
+
+	if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
+		AR5K_PRINTF("noise floor calibration failed (%uMHz)\n",
+			channel->freq);
+		return -EIO;
+	}
+	
+	hal->ah_calibration = false;
+
+	if (!(channel->val & CHANNEL_B)) {
+		hal->ah_calibration = true;
+		AR5K_REG_WRITE_BITS(hal, AR5K_PHY_IQ,
+		    AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
+		AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ,
+		    AR5K_PHY_IQ_RUN);
+	}
+
+	/*
+	 * Reset queues and start beacon timers at the end of the reset routine
+	 */
+	for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) {
+		/*No QCU on 5210*/
+		if (hal->ah_version != AR5K_AR5210)
+			AR5K_REG_WRITE_Q(hal, AR5K_QUEUE_QCUMASK(i), i);
+
+		if (ath5k_hw_reset_tx_queue(hal, i) == false) {
+			AR5K_PRINTF("failed to reset TX queue #%d\n", i);
+			return -EINVAL;
+		}
+	}
+
+	/* Pre-enable interrupts on 5211/5212*/
+	if (hal->ah_version != AR5K_AR5210) {
+		ath5k_hw_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_FATAL);
+	}
+
+	/*
+	 * Set RF kill flags if supported by the device (read from the EEPROM)
+	 * Disable gpio_intr for now since it results system hang.
+	 * TODO: Handle this in ath_intr
+	 */
+#if 0
+	if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) {
+		ath5k_hw_set_gpio_input(hal, 0);
+		if ((hal->ah_gpio[0] = ath5k_hw_get_gpio(hal, 0)) == 0)
+			ath5k_hw_set_gpio_intr(hal, 0, 1);
+		else
+			ath5k_hw_set_gpio_intr(hal, 0, 0);
+	}
+#endif
+
+	/*
+	 * Set the 32MHz reference clock on 5212 phy clock sleep register
+	 */
+	if (hal->ah_version == AR5K_AR5212) {
+		ath5k_hw_reg_write(hal, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR);
+		ath5k_hw_reg_write(hal, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
+		ath5k_hw_reg_write(hal, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL);
+		ath5k_hw_reg_write(hal, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
+		ath5k_hw_reg_write(hal, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
+		ath5k_hw_reg_write(hal, hal->ah_radio == AR5K_RF5111 ?
+			AR5K_PHY_SPENDING_RF5111 : AR5K_PHY_SPENDING_RF5112,
+			AR5K_PHY_SPENDING);
+	}
+
+	/* 
+	 * Disable beacons and reset the register
+	 */
+	AR5K_REG_DISABLE_BITS(hal, AR5K_BEACON,
+	    AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF);
+
+	return 0;
+}
+
+/*
+ * Reset chipset
+ */
+static int ath5k_hw_nic_reset(struct ath_hw *hal, u32 val)
+{
+	int ret;
+	u32 mask = val ? val : ~0;
+
+	AR5K_TRACE;
+
+	/* Read-and-clear RX Descriptor Pointer*/
+	ath5k_hw_reg_read(hal, AR5K_RXDP);
+
+	/*
+	 * Reset the device and wait until success
+	 */
+	ath5k_hw_reg_write(hal, val, AR5K_RESET_CTL);
+
+	/* Wait at least 128 PCI clocks */
+	udelay(15);
+
+	if (hal->ah_version == AR5K_AR5210) {
+		val &= AR5K_RESET_CTL_CHIP;
+		mask &= AR5K_RESET_CTL_CHIP;
+	} else {
+		val &=
+		    AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
+
+		mask &=
+		    AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
+	}
+
+	ret = ath5k_hw_register_timeout(hal, AR5K_RESET_CTL, mask, val, false);
+
+	/*
+	 * Reset configuration register (for hw byte-swap)
+	 */
+	if ((val & AR5K_RESET_CTL_PCU) == 0)
+		ath5k_hw_reg_write(hal, AR5K_INIT_CFG, AR5K_CFG);
+
+	return ret;
+}
+
+/*
+ * Power management functions
+ */
+
+/*
+ * Sleep control
+ */
+int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode,
+		bool set_chip, u16 sleep_duration)
+{
+	u32 staid;
+	int i;
+
+	AR5K_TRACE;
+	staid = ath5k_hw_reg_read(hal, AR5K_STA_ID1);
+
+	switch (mode) {
+	case AR5K_PM_AUTO:
+		staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
+		/* fallthrough */
+	case AR5K_PM_NETWORK_SLEEP:
+		if (set_chip == true) {
+			ath5k_hw_reg_write(hal,
+				AR5K_SLEEP_CTL_SLE | sleep_duration,
+				AR5K_SLEEP_CTL);
+		}
+		staid |= AR5K_STA_ID1_PWR_SV;
+		break;
+
+	case AR5K_PM_FULL_SLEEP:
+		if (set_chip == true) {
+			ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_SLP,
+				AR5K_SLEEP_CTL);
+		}
+		staid |= AR5K_STA_ID1_PWR_SV;
+		break;
+
+	case AR5K_PM_AWAKE:
+		if (set_chip == false)
+			goto commit;
+
+		ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_WAKE, AR5K_SLEEP_CTL);
+
+		for (i = 5000; i > 0; i--) {
+			/* Check if the chip did wake up */
+			if ((ath5k_hw_reg_read(hal, AR5K_PCICFG) &
+			    AR5K_PCICFG_SPWR_DN) == 0)
+				break;
+
+			/* Wait a bit and retry */
+			udelay(200);
+			ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_WAKE,
+				AR5K_SLEEP_CTL);
+		}
+
+		/* Fail if the chip didn't wake up */
+		if (i <= 0)
+			return -EIO;
+
+		staid &= ~AR5K_STA_ID1_PWR_SV;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+commit:
+	hal->ah_power_mode = mode;
+	ath5k_hw_reg_write(hal, staid, AR5K_STA_ID1);
+
+	return 0;
+}
+
+/*
+ * Get power mode (sleep state)
+ * TODO:Remove ?
+ */
+enum ath5k_power_mode
+ath5k_hw_get_power_mode(struct ath_hw *hal)
+{
+	AR5K_TRACE;
+	return hal->ah_power_mode;
+}
+
+
+
+
+/***********************\
+  DMA Related Functions
+\***********************/
+
+/*
+ * Receive functions
+ */
+
+/*
+ * Start DMA receive
+ */
+void ath5k_hw_start_rx(struct ath_hw *hal)
+{
+	AR5K_TRACE;
+	ath5k_hw_reg_write(hal, AR5K_CR_RXE, AR5K_CR);
+}
+
+/*
+ * Stop DMA receive
+ */
+int ath5k_hw_stop_rx_dma(struct ath_hw *hal)
+{
+	unsigned int i;
+
+	AR5K_TRACE;
+	ath5k_hw_reg_write(hal, AR5K_CR_RXD, AR5K_CR);
+
+	/*
+	 * It may take some time to disable the DMA receive unit
+	 */
+	for (i = 2000; i > 0 &&
+			(ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_CR_RXE) != 0;
+			i--)
+		udelay(10);
+
+	return i ? 0 : -EBUSY;
+}
+
+/*
+ * Get the address of the RX Descriptor
+ */
+u32 ath5k_hw_get_rx_buf(struct ath_hw *hal)
+{
+	return ath5k_hw_reg_read(hal, AR5K_RXDP);
+}
+
+/*
+ * Set the address of the RX Descriptor
+ */
+void ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr)
+{
+	AR5K_TRACE;
+
+	/*TODO:Shouldn't we check if RX is enabled first ?*/
+	ath5k_hw_reg_write(hal, phys_addr, AR5K_RXDP);
+}
+
+/*
+ * Transmit functions
+ */
+
+/*
+ * Start DMA transmit for a specific queue
+ * (see also QCU/DCU functions)
+ */
+int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue)
+{
+	u32 tx_queue;
+
+	AR5K_TRACE;
+	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
+
+	/* Return if queue is declared inactive */
+	if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
+		return -EIO;
+
+	if (hal->ah_version == AR5K_AR5210) {
+		tx_queue = ath5k_hw_reg_read(hal, AR5K_CR);
+
+		/*
+		 * Set the queue by type on 5210
+		 */
+		switch (hal->ah_txq[queue].tqi_type) {
+			case AR5K_TX_QUEUE_DATA:
+				tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
+				break;
+			case AR5K_TX_QUEUE_BEACON:
+				tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
+				ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | 
+					AR5K_BCR_BDMAE, AR5K_BSR);
+				break;
+			case AR5K_TX_QUEUE_CAB:
+				tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
+				ath5k_hw_reg_write(hal, AR5K_BCR_TQ1FV |
+					AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
+					AR5K_BSR);
+				break;
+			default:
+				return -EINVAL;
+		}
+		/* Start queue */
+		ath5k_hw_reg_write(hal, tx_queue, AR5K_CR);
+	} else {
+		/* Return if queue is disabled */
+		if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXD, queue))
+			return -EIO;
+
+		/* Start queue */
+		AR5K_REG_WRITE_Q(hal, AR5K_QCU_TXE, queue);
+	}
+
+	return 0;
+}
+
+/*
+ * Stop DMA transmit for a specific queue
+ * (see also QCU/DCU functions)
+ */
+bool
+ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue)
+{
+	int i = 100, pending;
+	u32 tx_queue;
+
+	AR5K_TRACE;
+	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
+
+	/* Return if queue is declared inactive */
+	if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
+		return false;
+
+	if (hal->ah_version == AR5K_AR5210) {
+		tx_queue = ath5k_hw_reg_read(hal, AR5K_CR);
+
+		/*
+		 * Set by queue type
+		 */
+		switch (hal->ah_txq[queue].tqi_type) {
+			case AR5K_TX_QUEUE_DATA:
+				tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
+				break;
+			case AR5K_TX_QUEUE_BEACON:
+			case AR5K_TX_QUEUE_CAB:
+				/* XXX Fix me... */
+				tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1;
+				ath5k_hw_reg_write(hal, 0, AR5K_BSR);
+				break;
+			default:
+				return false;
+		}
+
+		/* Stop queue */
+		ath5k_hw_reg_write(hal, tx_queue, AR5K_CR);
+	} else {
+		/*
+		 * Schedule TX disable and wait until queue is empty
+		 */
+		AR5K_REG_WRITE_Q(hal, AR5K_QCU_TXD, queue);
+
+		/*Check for pending frames*/
+		do {
+			pending = ath5k_hw_reg_read(hal, AR5K_QUEUE_STATUS(queue)) &
+						AR5K_QCU_STS_FRMPENDCNT;
+			udelay(100);
+		} while (--i && pending);
+
+		/* Clear register */
+		ath5k_hw_reg_write(hal, 0, AR5K_QCU_TXD);
+	}
+
+	/*TODO: Check for success else return false*/
+	return true;
+}
+
+/*
+ * Get the address of the TX Descriptor for a specific queue
+ * (see also QCU/DCU functions)
+ */ 
+u32
+ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue)
+{
+	u16 tx_reg;
+	AR5K_TRACE;
+	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
+
+	/*
+	 * Get the transmit queue descriptor pointer from the selected queue
+	 */
+	/*5210 doesn't have QCU*/
+	if (hal->ah_version == AR5K_AR5210) {
+		switch (hal->ah_txq[queue].tqi_type) {
+			case AR5K_TX_QUEUE_DATA:
+				tx_reg = AR5K_NOQCU_TXDP0;
+				break;
+			case AR5K_TX_QUEUE_BEACON:
+			case AR5K_TX_QUEUE_CAB:
+				tx_reg = AR5K_NOQCU_TXDP1;
+				break;
+			default:
+				return 0xffffffff;
+		}
+	} else {
+		tx_reg = AR5K_QUEUE_TXDP(queue);
+	}
+
+	return ath5k_hw_reg_read(hal, tx_reg);
+}
+
+/*
+ * Set the address of the TX Descriptor for a specific queue
+ * (see also QCU/DCU functions)
+ */
+int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr)
+{
+	u16 tx_reg;
+	AR5K_TRACE;
+	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
+
+	/*
+	 * Set the transmit queue descriptor pointer register by type
+	 * on 5210
+	 */
+	if (hal->ah_version == AR5K_AR5210) {
+		switch (hal->ah_txq[queue].tqi_type) {
+			case AR5K_TX_QUEUE_DATA:
+				tx_reg = AR5K_NOQCU_TXDP0;
+				break;
+			case AR5K_TX_QUEUE_BEACON:
+			case AR5K_TX_QUEUE_CAB:
+				tx_reg = AR5K_NOQCU_TXDP1;
+				break;
+			default:
+				return -EINVAL;
+		}
+	} else {
+		/*
+		 * Set the transmit queue descriptor pointer for 
+		 * the selected queue on QCU for 5211+
+		 * (this won't work if the queue is still active)
+		 */
+		if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXE, queue))
+			return -EIO;
+
+		tx_reg = AR5K_QUEUE_TXDP(queue);
+	}
+
+	/* Set descriptor pointer */
+	ath5k_hw_reg_write(hal, phys_addr, tx_reg);
+
+	return 0;
+}
+
+/*
+ * Update tx trigger level
+ */
+bool
+ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase)
+{
+	u32 trigger_level, imr;
+	bool status = false;
+	AR5K_TRACE;
+
+	/*
+	 * Disable interrupts by setting the mask
+	 */
+	imr = ath5k_hw_set_intr(hal, hal->ah_imr & ~AR5K_INT_GLOBAL);
+
+	/*TODO: Boundary check on trigger_level*/
+	trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TXCFG),
+			AR5K_TXCFG_TXFULL);
+
+	if (increase == false) {
+		if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
+			goto done;
+	} else
+		trigger_level +=
+			((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);
+
+	/*
+	 * Update trigger level on success
+	 */
+	if (hal->ah_version == AR5K_AR5210)
+		ath5k_hw_reg_write(hal, trigger_level, AR5K_TRIG_LVL);
+	else
+		AR5K_REG_WRITE_BITS(hal, AR5K_TXCFG,
+				AR5K_TXCFG_TXFULL, trigger_level);
+
+	status = true;
+
+ done:
+	/*
+	 * Restore interrupt mask
+	 */
+	ath5k_hw_set_intr(hal, imr);
+
+	return status;
+}
+
+/*
+ * Interrupt handling
+ */
+
+/*
+ * Check if we have pending interrupts
+ */
+bool ath5k_hw_is_intr_pending(struct ath_hw *hal)
+{
+	AR5K_TRACE;
+	return ath5k_hw_reg_read(hal, AR5K_INTPEND);
+}
+
+/*
+ * Get interrupt mask (ISR)
+ */
+int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask)
+{
+	u32 data;
+
+	AR5K_TRACE;
+
+	/*
+	 * Read interrupt status from the Interrupt Status register
+	 * on 5210
+	 */
+	if (hal->ah_version == AR5K_AR5210) {
+		data = ath5k_hw_reg_read(hal, AR5K_ISR);
+		if (data == AR5K_INT_NOCARD) {
+			*interrupt_mask = data;
+			return -ENODEV;
+		}
+	}
+
+	/*
+	 * Read interrupt status from the Read-And-Clear shadow register
+	 */
+	data = ath5k_hw_reg_read(hal, AR5K_RAC_PISR);
+
+	/*
+	 * Get abstract interrupt mask (HAL-compatible)
+	 */
+	*interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr;
+
+	if (data == AR5K_INT_NOCARD)
+		return -ENODEV;
+
+	if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR))
+		*interrupt_mask |= AR5K_INT_RX;
+
+	if (data & (AR5K_ISR_TXOK | AR5K_ISR_TXERR))
+		*interrupt_mask |= AR5K_INT_TX;
+
+	if (hal->ah_version != AR5K_AR5210) {
+		/*HIU = Host Interface Unit (PCI etc)*/
+		if (data & (AR5K_ISR_HIUERR))
+			*interrupt_mask |= AR5K_INT_FATAL;
+
+		/*Beacon Not Ready*/
+		if (data & (AR5K_ISR_BNR))
+			*interrupt_mask |= AR5K_INT_BNR;
+	}
+
+	/* 
+	 * XXX: BMISS interrupts may occur after association. 
+	 * I found this on 5210 code but it needs testing
+	 */
+#if 0
+	interrupt_mask &= ~AR5K_INT_BMISS;
+#endif
+
+	/*
+	 * In case we didn't handle anything,
+	 * print the register value.
+	 */
+	if (*interrupt_mask == 0 && printk_ratelimit())
+		AR5K_PRINTF("0x%08x\n", data);
+
+	return 0;
+}
+
+/*
+ * Set interrupt mask
+ */
+enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask)
+{
+	enum ath5k_int old_mask, int_mask;
+
+	/*
+	 * Disable card interrupts to prevent any race conditions
+	 * (they will be re-enabled afterwards).
+	 */
+	ath5k_hw_reg_write(hal, AR5K_IER_DISABLE, AR5K_IER);
+
+	old_mask = hal->ah_imr;
+
+	/*
+	 * Add additional, chipset-dependent interrupt mask flags
+	 * and write them to the IMR (interrupt mask register).
+	 */
+	int_mask = new_mask & AR5K_INT_COMMON;
+
+	if (new_mask & AR5K_INT_RX)
+		int_mask |= AR5K_IMR_RXOK | AR5K_IMR_RXERR | AR5K_IMR_RXORN |
+			AR5K_IMR_RXDESC;
+
+	if (new_mask & AR5K_INT_TX)
+		int_mask |= AR5K_IMR_TXOK | AR5K_IMR_TXERR | AR5K_IMR_TXDESC |
+			AR5K_IMR_TXURN;
+
+	if (hal->ah_version != AR5K_AR5210) {
+		if (new_mask & AR5K_INT_FATAL) {
+			int_mask |= AR5K_IMR_HIUERR;
+			AR5K_REG_ENABLE_BITS(hal, AR5K_SIMR2, AR5K_SIMR2_MCABT |
+					AR5K_SIMR2_SSERR | AR5K_SIMR2_DPERR);
+		}
+	}
+
+	ath5k_hw_reg_write(hal, int_mask, AR5K_PIMR);
+
+	/* Store new interrupt mask */
+	hal->ah_imr = new_mask;
+
+	/* ..re-enable interrupts */
+	ath5k_hw_reg_write(hal, AR5K_IER_ENABLE, AR5K_IER);
+
+	return old_mask;
+}
+
+/*
+ * Enalbe HW radar detection
+ */
+void
+ath5k_hw_radar_alert(struct ath_hw *hal, bool enable)
+{
+
+	AR5K_TRACE;
+	/*
+	 * Enable radar detection
+	 */
+
+	/*Disable interupts*/
+	ath5k_hw_reg_write(hal, AR5K_IER_DISABLE, AR5K_IER);
+
+	/*
+	 * Set the RXPHY interrupt to be able to detect
+	 * possible radar activity.
+	 */
+	if (hal->ah_version == AR5K_AR5210) {
+		if (enable == true) {
+			AR5K_REG_ENABLE_BITS(hal, AR5K_IMR,
+					AR5K_IMR_RXPHY);
+		} else {
+			AR5K_REG_DISABLE_BITS(hal, AR5K_IMR,
+					AR5K_IMR_RXPHY);
+		}
+	} else {
+		/*Also set AR5K_PHY_RADAR register on 5111/5112*/
+		if (enable == true) {
+			ath5k_hw_reg_write(hal, AR5K_PHY_RADAR_ENABLE,
+				AR5K_PHY_RADAR);
+			AR5K_REG_ENABLE_BITS(hal, AR5K_PIMR,
+				AR5K_IMR_RXPHY);
+		} else {
+			ath5k_hw_reg_write(hal, AR5K_PHY_RADAR_DISABLE,
+				AR5K_PHY_RADAR);
+			AR5K_REG_DISABLE_BITS(hal, AR5K_PIMR,
+				AR5K_IMR_RXPHY);
+		}
+	}
+
+	/*Re-enable interrupts*/
+	ath5k_hw_reg_write(hal, AR5K_IER_ENABLE, AR5K_IER);
+}
+
+
+
+
+/*************************\
+  EEPROM access functions
+\*************************/
+
+/*
+ * Read from eeprom
+ */
+static int ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data)
+{
+	u32 status, timeout;
+
+	AR5K_TRACE;
+	/*
+	 * Initialize EEPROM access
+	 */
+	if (hal->ah_version == AR5K_AR5210) {
+		AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_EEAE);
+		(void)ath5k_hw_reg_read(hal, AR5K_EEPROM_BASE + (4 * offset));
+	} else {
+		ath5k_hw_reg_write(hal, offset, AR5K_EEPROM_BASE);
+		AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD,
+				AR5K_EEPROM_CMD_READ);
+	}
+
+	for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
+		status = ath5k_hw_reg_read(hal, AR5K_EEPROM_STATUS);
+		if (status & AR5K_EEPROM_STAT_RDDONE) {
+			if (status & AR5K_EEPROM_STAT_RDERR)
+				return -EIO;
+			*data = (u16)
+			    (ath5k_hw_reg_read(hal, AR5K_EEPROM_DATA) & 0xffff);
+			return 0;
+		}
+		udelay(15);
+	}
+
+	return -ETIMEDOUT;
+}
+
+/*
+ * Write to eeprom - currently disabled, use at your own risk
+ */
+static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data)
+{
+#if 0
+	u32 status, timeout;
+
+	AR5K_TRACE;
+
+	/*
+	 * Initialize eeprom access
+	 */
+
+	if (hal->ah_version == AR5K_AR5210) {
+		AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_EEAE);
+	} else {
+		AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_RESET);
+	}
+
+	/*
+	 * Write data to data register
+	 */
+
+	if (hal->ah_version == AR5K_AR5210) {
+		ath5k_hw_reg_write(hal, data, AR5K_EEPROM_BASE + (4 * offset));
+	} else {
+		ath5k_hw_reg_write(hal, offset, AR5K_EEPROM_BASE);
+		ath5k_hw_reg_write(hal, data, AR5K_EEPROM_DATA);
+		AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_WRITE);
+	}
+
+	/*
+	 * Check status
+	 */
+
+	for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
+		status = ath5k_hw_reg_read(hal, AR5K_EEPROM_STATUS);
+		if (status & AR5K_EEPROM_STAT_WRDONE) {
+			if (status & AR5K_EEPROM_STAT_WRERR)
+				return EIO;
+			return 0;
+		}
+		udelay(15);
+	}
+#endif
+	AR5K_PRINTF("EEPROM Write is disabled!");
+	return -EIO;
+}
+
+u16
+ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode)
+{
+	u16 val;
+
+	if (bin == AR5K_EEPROM_CHANNEL_DIS)
+		return bin;
+
+	if (mode == AR5K_EEPROM_MODE_11A) {
+		if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
+			val = (5 * bin) + 4800;
+		else
+			val = bin > 62 ?
+			    (10 * 62) + (5 * (bin - 62)) + 5100 :
+			    (bin * 10) + 5100;
+	} else {
+		if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
+			val = bin + 2300;
+		else
+			val = bin + 2400;
+	}
+
+	return val;
+}
+
+/*
+ * Read antenna infos from eeprom
+ */
+int
+ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode)
+{
+	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
+	u32 o = *offset;
+	u16 val;
+	int ret, i = 0;
+
+	AR5K_EEPROM_READ(o++, val);
+	ee->ee_switch_settling[mode]	= (val >> 8) & 0x7f;
+	ee->ee_ant_tx_rx[mode]		= (val >> 2) & 0x3f;
+	ee->ee_ant_control[mode][i]	= (val << 4) & 0x3f;
+
+	AR5K_EEPROM_READ(o++, val);
+	ee->ee_ant_control[mode][i++]	|= (val >> 12) & 0xf;
+	ee->ee_ant_control[mode][i++]	= (val >> 6) & 0x3f;
+	ee->ee_ant_control[mode][i++]	= val & 0x3f;
+
+	AR5K_EEPROM_READ(o++, val);
+	ee->ee_ant_control[mode][i++]	= (val >> 10) & 0x3f;
+	ee->ee_ant_control[mode][i++]	= (val >> 4) & 0x3f;
+	ee->ee_ant_control[mode][i]	= (val << 2) & 0x3f;
+
+	AR5K_EEPROM_READ(o++, val);
+	ee->ee_ant_control[mode][i++]	|= (val >> 14) & 0x3;
+	ee->ee_ant_control[mode][i++]	= (val >> 8) & 0x3f;
+	ee->ee_ant_control[mode][i++]	= (val >> 2) & 0x3f;
+	ee->ee_ant_control[mode][i]	= (val << 4) & 0x3f;
+
+	AR5K_EEPROM_READ(o++, val);
+	ee->ee_ant_control[mode][i++]	|= (val >> 12) & 0xf;
+	ee->ee_ant_control[mode][i++]	= (val >> 6) & 0x3f;
+	ee->ee_ant_control[mode][i++]	= val & 0x3f;
+
+	/* Get antenna modes */
+	hal->ah_antenna[mode][0] =
+	    (ee->ee_ant_control[mode][0] << 4) | 0x1;
+	hal->ah_antenna[mode][AR5K_ANT_FIXED_A] =
+	     ee->ee_ant_control[mode][1] 	|
+	    (ee->ee_ant_control[mode][2] << 6) 	|
+	    (ee->ee_ant_control[mode][3] << 12) |
+	    (ee->ee_ant_control[mode][4] << 18) |
+	    (ee->ee_ant_control[mode][5] << 24);
+	hal->ah_antenna[mode][AR5K_ANT_FIXED_B] =
+	     ee->ee_ant_control[mode][6] 	|
+	    (ee->ee_ant_control[mode][7] << 6) 	|
+	    (ee->ee_ant_control[mode][8] << 12) |
+	    (ee->ee_ant_control[mode][9] << 18) |
+	    (ee->ee_ant_control[mode][10] << 24);
+
+	/* return new offset */
+	*offset = o;
+
+	return 0;
+}
+
+/*
+ * Read supported modes from eeprom
+ */
+int
+ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode)
+{
+	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
+	u32 o = *offset;
+	u16 val;
+	int ret;
+
+	AR5K_EEPROM_READ(o++, val);
+	ee->ee_tx_end2xlna_enable[mode]	= (val >> 8) & 0xff;
+	ee->ee_thr_62[mode]		= val & 0xff;
+
+	if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
+		ee->ee_thr_62[mode] =
+		    mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
+
+	AR5K_EEPROM_READ(o++, val);
+	ee->ee_tx_end2xpa_disable[mode]	= (val >> 8) & 0xff;
+	ee->ee_tx_frm2xpa_enable[mode]	= val & 0xff;
+
+	AR5K_EEPROM_READ(o++, val);
+	ee->ee_pga_desired_size[mode]	= (val >> 8) & 0xff;
+
+	if ((val & 0xff) & 0x80)
+		ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
+	else
+		ee->ee_noise_floor_thr[mode] = val & 0xff;
+
+	if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
+		ee->ee_noise_floor_thr[mode] =
+		    mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
+
+	AR5K_EEPROM_READ(o++, val);
+	ee->ee_xlna_gain[mode]		= (val >> 5) & 0xff;
+	ee->ee_x_gain[mode]		= (val >> 1) & 0xf;
+	ee->ee_xpd[mode]		= val & 0x1;
+
+	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
+		ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
+
+	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
+		AR5K_EEPROM_READ(o++, val);
+		ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
+
+		if (mode == AR5K_EEPROM_MODE_11A)
+			ee->ee_xr_power[mode] = val & 0x3f;
+		else {
+			ee->ee_ob[mode][0] = val & 0x7;
+			ee->ee_db[mode][0] = (val >> 3) & 0x7;
+		}
+	}
+
+	if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
+		ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
+		ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
+	} else {
+		ee->ee_i_gain[mode] = (val >> 13) & 0x7;
+
+		AR5K_EEPROM_READ(o++, val);
+		ee->ee_i_gain[mode] |= (val << 3) & 0x38;
+
+		if (mode == AR5K_EEPROM_MODE_11G)
+			ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
+	}
+
+	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
+	    mode == AR5K_EEPROM_MODE_11A) {
+		ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
+		ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
+	}
+
+	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 &&
+	    mode == AR5K_EEPROM_MODE_11G)
+		ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
+
+	/* return new offset */
+	*offset = o;
+
+	return 0;
+}
+
+/*
+ * Initialize eeprom & capabilities structs
+ */
+static int ath5k_eeprom_init(struct ath_hw *hal)
+{
+	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
+	u32 offset;
+	u16 val;
+	int ret, i;
+	unsigned int mode;
+
+	/* Initial TX thermal adjustment values */
+	ee->ee_tx_clip = 4;
+	ee->ee_pwd_84 = ee->ee_pwd_90 = 1;
+	ee->ee_gain_select = 1;
+
+	/*
+	 * Read values from EEPROM and store them in the capability structure
+	 */
+	AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
+	AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
+	AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
+	AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
+	AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
+
+	/* Return if we have an old EEPROM */
+	if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
+		return 0;
+
+#ifdef notyet
+	/*
+	 * Validate the checksum of the EEPROM date. There are some
+	 * devices with invalid EEPROMs.
+	 */
+	for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) {
+		AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
+		cksum ^= val;
+	}
+	if (cksum != AR5K_EEPROM_INFO_CKSUM) {
+		AR5K_PRINTF("Invalid EEPROM checksum 0x%04x\n", cksum);
+		return -EIO;
+	}
+#endif
+
+	AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(hal->ah_ee_version),
+	    ee_ant_gain);
+
+	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
+		AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
+		AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
+	}
+
+	if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
+		AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
+		ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
+		ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
+
+		AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
+		ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
+		ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
+	}
+
+	/*
+	 * Get conformance test limit values
+	 */
+	offset = AR5K_EEPROM_CTL(hal->ah_ee_version);
+	ee->ee_ctls = AR5K_EEPROM_N_CTLS(hal->ah_ee_version);
+
+	for (i = 0; i < ee->ee_ctls; i++) {
+		AR5K_EEPROM_READ(offset++, val);
+		ee->ee_ctl[i] = (val >> 8) & 0xff;
+		ee->ee_ctl[i + 1] = val & 0xff;
+	}
+
+	/*
+	 * Get values for 802.11a (5GHz)
+	 */
+	mode = AR5K_EEPROM_MODE_11A;
+
+	ee->ee_turbo_max_power[mode] =
+	    AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
+
+	offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version);
+
+	ret = ath5k_eeprom_read_ants(hal, &offset, mode);
+	if (ret)
+		return ret;
+
+	AR5K_EEPROM_READ(offset++, val);
+	ee->ee_adc_desired_size[mode]	= (s8)((val >> 8) & 0xff);
+	ee->ee_ob[mode][3]		= (val >> 5) & 0x7;
+	ee->ee_db[mode][3]		= (val >> 2) & 0x7;
+	ee->ee_ob[mode][2]		= (val << 1) & 0x7;
+
+	AR5K_EEPROM_READ(offset++, val);
+	ee->ee_ob[mode][2]		|= (val >> 15) & 0x1;
+	ee->ee_db[mode][2]		= (val >> 12) & 0x7;
+	ee->ee_ob[mode][1]		= (val >> 9) & 0x7;
+	ee->ee_db[mode][1]		= (val >> 6) & 0x7;
+	ee->ee_ob[mode][0]		= (val >> 3) & 0x7;
+	ee->ee_db[mode][0]		= val & 0x7;
+
+	ret = ath5k_eeprom_read_modes(hal, &offset, mode);
+	if (ret)
+		return ret;
+
+	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
+		AR5K_EEPROM_READ(offset++, val);
+		ee->ee_margin_tx_rx[mode] = val & 0x3f;
+	}
+
+	/*
+	 * Get values for 802.11b (2.4GHz)
+	 */
+	mode = AR5K_EEPROM_MODE_11B;
+	offset = AR5K_EEPROM_MODES_11B(hal->ah_ee_version);
+
+	ret = ath5k_eeprom_read_ants(hal, &offset, mode);
+	if (ret)
+		return ret;
+
+	AR5K_EEPROM_READ(offset++, val);
+	ee->ee_adc_desired_size[mode]	= (s8)((val >> 8) & 0xff);
+	ee->ee_ob[mode][1]		= (val >> 4) & 0x7;
+	ee->ee_db[mode][1]		= val & 0x7;
+
+	ret = ath5k_eeprom_read_modes(hal, &offset, mode);
+	if (ret)
+		return ret;
+
+	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
+		AR5K_EEPROM_READ(offset++, val);
+		ee->ee_cal_pier[mode][0] =
+		    ath5k_eeprom_bin2freq(hal, val & 0xff, mode);
+		ee->ee_cal_pier[mode][1] =
+		    ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
+
+		AR5K_EEPROM_READ(offset++, val);
+		ee->ee_cal_pier[mode][2] =
+		    ath5k_eeprom_bin2freq(hal, val & 0xff, mode);
+	}
+
+	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
+		ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
+	}
+
+	/*
+	 * Get values for 802.11g (2.4GHz)
+	 */
+	mode = AR5K_EEPROM_MODE_11G;
+	offset = AR5K_EEPROM_MODES_11G(hal->ah_ee_version);
+
+	ret = ath5k_eeprom_read_ants(hal, &offset, mode);
+	if (ret)
+		return ret;
+
+	AR5K_EEPROM_READ(offset++, val);
+	ee->ee_adc_desired_size[mode]	= (s8)((val >> 8) & 0xff);
+	ee->ee_ob[mode][1]		= (val >> 4) & 0x7;
+	ee->ee_db[mode][1]		= val & 0x7;
+
+	ret = ath5k_eeprom_read_modes(hal, &offset, mode);
+	if (ret)
+		return ret;
+
+	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
+		AR5K_EEPROM_READ(offset++, val);
+		ee->ee_cal_pier[mode][0] =
+		    ath5k_eeprom_bin2freq(hal, val & 0xff, mode);
+		ee->ee_cal_pier[mode][1] =
+		    ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
+
+		AR5K_EEPROM_READ(offset++, val);
+		ee->ee_turbo_max_power[mode] = val & 0x7f;
+		ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
+
+		AR5K_EEPROM_READ(offset++, val);
+		ee->ee_cal_pier[mode][2] =
+		    ath5k_eeprom_bin2freq(hal, val & 0xff, mode);
+
+		if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
+			ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
+		}
+
+		AR5K_EEPROM_READ(offset++, val);
+		ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
+		ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
+
+		if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
+			AR5K_EEPROM_READ(offset++, val);
+			ee->ee_cck_ofdm_gain_delta = val & 0xff;
+		}
+	}
+
+	/*
+	 * Read 5GHz EEPROM channels
+	 */
+
+	return 0;
+}
+
+/*
+ * Read the MAC address from eeprom
+ */
+static int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac)
+{
+	u8 mac_d[ETH_ALEN];
+	u32 total, offset;
+	u16 data;
+	int octet, ret;
+
+	memset(mac, 0, ETH_ALEN);
+	memset(mac_d, 0, ETH_ALEN);
+
+	ret = ath5k_hw_eeprom_read(hal, 0x20, &data);
+	if (ret)
+		return ret;
+
+	for (offset = 0x1f, octet = 0, total = 0;
+	     offset >= 0x1d; offset--) {
+		ret = ath5k_hw_eeprom_read(hal, offset, &data);
+		if (ret)
+			return ret;
+
+		total += data;
+		mac_d[octet + 1] = data & 0xff;
+		mac_d[octet] = data >> 8;
+		octet += 2;
+	}
+
+	memcpy(mac, mac_d, ETH_ALEN);
+
+	if (!total || total == 3 * 0xffff)
+		return -EINVAL;
+
+	return 0;
+}
+
+/*
+ * Read/Write regulatory domain
+ */
+static bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write,
+	enum ieee80211_regdomain *regdomain)
+{
+	u16 ee_regdomain;
+
+	/* Read current value */
+	if (write != true) {
+		ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain;
+		*regdomain = ath5k_regdomain_to_ieee(ee_regdomain);
+		return true;
+	}
+
+	ee_regdomain = ath5k_regdomain_from_ieee(*regdomain);
+
+	/* Try to write a new value */
+	if (hal->ah_capabilities.cap_eeprom.ee_protect &
+	    AR5K_EEPROM_PROTECT_WR_128_191)
+		return false;
+	if (ath5k_hw_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN,
+	    ee_regdomain) != 0)
+		return false;
+
+	hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain;
+
+	return true;
+}
+
+/*
+ * Use the above to write a new regulatory domain
+ */
+int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain)
+{
+	enum ieee80211_regdomain ieee_regdomain;
+
+	ieee_regdomain = ath5k_regdomain_to_ieee(regdomain);
+
+	if (ath5k_eeprom_regulation_domain(hal, true, &ieee_regdomain) == true)
+		return 0;
+
+	return -EIO;
+}
+
+/*
+ * Fill the capabilities struct
+ */
+static int ath5k_hw_get_capabilities(struct ath_hw *hal)
+{
+	u16 ee_header;
+
+	AR5K_TRACE;
+	/* Capabilities stored in the EEPROM */
+	ee_header = hal->ah_capabilities.cap_eeprom.ee_header;
+
+	if (hal->ah_version == AR5K_AR5210) {
+		/*
+		 * Set radio capabilities
+		 * (The AR5110 only supports the middle 5GHz band)
+		 */
+		hal->ah_capabilities.cap_range.range_5ghz_min = 5120;
+		hal->ah_capabilities.cap_range.range_5ghz_max = 5430;
+		hal->ah_capabilities.cap_range.range_2ghz_min = 0;
+		hal->ah_capabilities.cap_range.range_2ghz_max = 0;
+
+		/* Set supported modes */
+		set_bit(MODE_IEEE80211A, hal->ah_capabilities.cap_mode);
+		set_bit(MODE_ATHEROS_TURBO, hal->ah_capabilities.cap_mode);
+	} else {
+		/*
+		 * XXX The tranceiver supports frequencies from 4920 to 6100GHz
+		 * XXX and from 2312 to 2732GHz. There are problems with the current
+		 * XXX ieee80211 implementation because the IEEE channel mapping
+		 * XXX does not support negative channel numbers (2312MHz is channel
+		 * XXX -19). Of course, this doesn't matter because these channels
+		 * XXX are out of range but some regulation domains like MKK (Japan)
+		 * XXX will support frequencies somewhere around 4.8GHz.
+		 */
+
+		/*
+		 * Set radio capabilities
+		 */
+
+		if (AR5K_EEPROM_HDR_11A(ee_header)) {
+			hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */
+			hal->ah_capabilities.cap_range.range_5ghz_max = 6100;
+	
+			/* Set supported modes */
+			set_bit(MODE_IEEE80211A, hal->ah_capabilities.cap_mode);
+			set_bit(MODE_ATHEROS_TURBO,
+					hal->ah_capabilities.cap_mode);
+			if (hal->ah_version == AR5K_AR5212)
+				set_bit(MODE_ATHEROS_TURBOG,
+						hal->ah_capabilities.cap_mode);
+		}
+	
+		/* Enable  802.11b if a 2GHz capable radio (2111/5112) is connected */
+		if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) {
+			hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
+			hal->ah_capabilities.cap_range.range_2ghz_max = 2732;
+	
+			if (AR5K_EEPROM_HDR_11B(ee_header))
+				set_bit(MODE_IEEE80211B,
+						hal->ah_capabilities.cap_mode);
+
+			if (AR5K_EEPROM_HDR_11G(ee_header))
+				set_bit(MODE_IEEE80211G,
+						hal->ah_capabilities.cap_mode);
+		}
+	}
+
+	/* GPIO */
+	hal->ah_gpio_npins = AR5K_NUM_GPIO;
+
+	/* Set number of supported TX queues */
+	if (hal->ah_version == AR5K_AR5210)
+		hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES_NOQCU;
+	else
+		hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
+
+	return 0;
+}
+
+/*********************************\
+  Protocol Control Unit Functions
+\*********************************/
+
+/*
+ * Set Operation mode
+ */
+void
+ath5k_hw_set_opmode(struct ath_hw *hal)
+{
+	u32 pcu_reg, beacon_reg, low_id, high_id;
+
+	pcu_reg = 0;
+	beacon_reg = 0;
+
+	AR5K_TRACE;
+
+	switch (hal->ah_op_mode) {
+	case IEEE80211_IF_TYPE_IBSS:
+		pcu_reg |= AR5K_STA_ID1_ADHOC |
+			AR5K_STA_ID1_DESC_ANTENNA |
+			(hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0);
+
+		beacon_reg |= AR5K_BCR_ADHOC;
+		break;
+
+	case IEEE80211_IF_TYPE_AP:
+		pcu_reg |= AR5K_STA_ID1_AP |
+			AR5K_STA_ID1_RTS_DEF_ANTENNA |
+			(hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0);
+
+		beacon_reg |= AR5K_BCR_AP;
+		break;
+
+	case IEEE80211_IF_TYPE_STA:
+		pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
+			(hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_PWR_SV :0);
+	case IEEE80211_IF_TYPE_MNTR:
+		pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
+			(hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0);
+		break;
+
+	default:
+		return;
+	}
+
+	/*
+	 * Set PCU registers
+	 */
+	low_id = AR5K_LOW_ID(hal->ah_sta_id);
+	high_id = AR5K_HIGH_ID(hal->ah_sta_id);
+	ath5k_hw_reg_write(hal, low_id, AR5K_STA_ID0);
+	ath5k_hw_reg_write(hal, pcu_reg | high_id, AR5K_STA_ID1);
+
+	/*
+	 * Set Beacon Control Register on 5210
+	 */
+	if (hal->ah_version == AR5K_AR5210)
+		ath5k_hw_reg_write(hal, beacon_reg, AR5K_BCR);
+}
+
+/*
+ * BSSID Functions
+ */
+
+/*
+ * Get station id
+ */
+void
+ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac)
+{
+	AR5K_TRACE;
+	memcpy(mac, hal->ah_sta_id, ETH_ALEN);
+}
+
+/*
+ * Set station id
+ */
+bool
+ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac)
+{
+	u32 low_id, high_id;
+
+	AR5K_TRACE;
+	/* Set new station ID */
+	memcpy(hal->ah_sta_id, mac, ETH_ALEN);
+
+	low_id = AR5K_LOW_ID(mac);
+	high_id = AR5K_HIGH_ID(mac);
+
+	ath5k_hw_reg_write(hal, low_id, AR5K_STA_ID0);
+	ath5k_hw_reg_write(hal, high_id, AR5K_STA_ID1);
+
+	return true;
+}
+
+/*
+ * Set BSSID
+ */
+void
+ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid,
+    u16 assoc_id)
+{
+	u32 low_id, high_id;
+	u16 tim_offset = 0;
+
+	/*
+	 * Set simple BSSID mask on 5212
+	 */
+	if (hal->ah_version == AR5K_AR5212) {
+		ath5k_hw_reg_write(hal, 0xfffffff, AR5K_BSS_IDM0);
+		ath5k_hw_reg_write(hal, 0xfffffff, AR5K_BSS_IDM1);
+	}
+
+	/*
+	 * Set BSSID which triggers the "SME Join" operation
+	 */
+	low_id = AR5K_LOW_ID(bssid);
+	high_id = AR5K_HIGH_ID(bssid);
+	ath5k_hw_reg_write(hal, low_id, AR5K_BSS_ID0);
+	ath5k_hw_reg_write(hal, high_id | ((assoc_id & 0x3fff) <<
+				AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1);
+	memcpy(&hal->ah_bssid, bssid, ETH_ALEN);
+
+	if (assoc_id == 0) {
+		ath5k_hw_disable_pspoll(hal);
+		return;
+	}
+
+	AR5K_REG_WRITE_BITS(hal, AR5K_BEACON, AR5K_BEACON_TIM,
+	    tim_offset ? tim_offset + 4 : 0);
+
+	ath5k_hw_enable_pspoll(hal, NULL, 0);
+}
+
+/*
+ * Set BSSID mask on 5212
+ */
+bool
+ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask)
+{
+	u32 low_id, high_id;
+	AR5K_TRACE;
+
+	if (hal->ah_version == AR5K_AR5212) {
+
+		low_id = AR5K_LOW_ID(mask);
+		high_id = AR5K_HIGH_ID(mask);
+
+		ath5k_hw_reg_write(hal, low_id, AR5K_BSS_IDM0); 
+		ath5k_hw_reg_write(hal, high_id, AR5K_BSS_IDM1); 
+
+		return true; 
+	} else
+		return false;
+}
+
+/*
+ * Receive start/stop functions
+ */
+
+/*
+ * Start receive on PCU
+ */
+void
+ath5k_hw_start_rx_pcu(struct ath_hw *hal)
+{
+	AR5K_TRACE;
+	AR5K_REG_DISABLE_BITS(hal, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
+}
+
+/*
+ * Stop receive on PCU
+ */
+void
+ath5k_hw_stop_pcu_recv(struct ath_hw *hal)
+{
+	AR5K_TRACE;
+	AR5K_REG_ENABLE_BITS(hal, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
+}
+
+/*
+ * RX Filter functions
+ */
+
+/*
+ * Set multicast filter
+ */
+void
+ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0,
+    u32 filter1)
+{
+	AR5K_TRACE;
+	/* Set the multicat filter */
+	ath5k_hw_reg_write(hal, filter0, AR5K_MCAST_FILTER0);
+	ath5k_hw_reg_write(hal, filter1, AR5K_MCAST_FILTER1);
+}
+
+/*
+ * Set multicast filter by index
+ */
+bool
+ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index)
+{
+
+	AR5K_TRACE;
+	if (index >= 64)
+	    return false;
+	else if (index >= 32)
+	    AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER1,
+		(1 << (index - 32)));
+	else
+	    AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER0,
+		(1 << index));
+
+	return true;
+}
+
+/*
+ * Clear Multicast filter by index
+ */
+bool
+ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index)
+{
+
+	AR5K_TRACE;
+	if (index >= 64)
+	    return false;
+	else if (index >= 32)
+	    AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER1,
+		(1 << (index - 32)));
+	else
+	    AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER0,
+		(1 << index));
+
+	return true;
+}
+
+/*
+ * Get current rx filter
+ */
+u32
+ath5k_hw_get_rx_filter(struct ath_hw *hal)
+{
+	u32 data, filter = 0;
+
+	AR5K_TRACE;
+	filter = ath5k_hw_reg_read(hal, AR5K_RX_FILTER);
+
+	/*Radar detection for 5212*/
+	if (hal->ah_version == AR5K_AR5212) {
+		data = ath5k_hw_reg_read(hal, AR5K_PHY_ERR_FIL);
+
+		if (data & AR5K_PHY_ERR_FIL_RADAR)
+			filter |= AR5K_RX_FILTER_PHYRADAR;
+		if (data & (AR5K_PHY_ERR_FIL_OFDM |
+			AR5K_PHY_ERR_FIL_CCK))
+			filter |= AR5K_RX_FILTER_PHYERR;
+	}
+
+	return filter;
+}
+
+/*
+ * Set rx filter
+ */
+void
+ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter)
+{
+	u32 data = 0;
+
+	AR5K_TRACE;
+
+	/* Set PHY error filter register on 5212*/
+	if (hal->ah_version == AR5K_AR5212) {
+		if (filter & AR5K_RX_FILTER_PHYRADAR)
+			data |= AR5K_PHY_ERR_FIL_RADAR;
+		if (filter & AR5K_RX_FILTER_PHYERR)
+			data |= AR5K_PHY_ERR_FIL_OFDM |
+				AR5K_PHY_ERR_FIL_CCK;
+	}
+
+	/*
+	 * The AR5210 uses promiscous mode to detect radar activity
+	 */
+	if ((hal->ah_version == AR5K_AR5210) && 
+			(filter & AR5K_RX_FILTER_PHYRADAR)) {
+		filter &= ~AR5K_RX_FILTER_PHYRADAR;
+		filter |= AR5K_RX_FILTER_PROM;
+	}
+
+	/*Zero length DMA*/
+	if (data)
+		AR5K_REG_ENABLE_BITS(hal, AR5K_RXCFG,
+				AR5K_RXCFG_ZLFDMA);
+	else
+		AR5K_REG_DISABLE_BITS(hal, AR5K_RXCFG,
+				AR5K_RXCFG_ZLFDMA);
+
+	/*Write RX Filter register*/
+	ath5k_hw_reg_write(hal, filter & 0xff, AR5K_RX_FILTER);
+
+	/*Write PHY error filter register on 5212*/
+	if (hal->ah_version == AR5K_AR5212)
+		ath5k_hw_reg_write(hal, data, AR5K_PHY_ERR_FIL);
+
+}
+
+/*
+ * Beacon related functions
+ */
+
+/*
+ * Get a 32bit TSF
+ */
+u32 ath5k_hw_get_tsf32(struct ath_hw *hal)
+{
+	AR5K_TRACE;
+	return ath5k_hw_reg_read(hal, AR5K_TSF_L32);
+}
+
+/*
+ * Get the full 64bit TSF
+ */
+u64 ath5k_hw_get_tsf64(struct ath_hw *hal)
+{
+	u64 tsf = ath5k_hw_reg_read(hal, AR5K_TSF_U32);
+	AR5K_TRACE;
+
+	return ath5k_hw_reg_read(hal, AR5K_TSF_L32) | (tsf << 32);
+}
+
+/*
+ * Force a TSF reset
+ */
+void ath5k_hw_reset_tsf(struct ath_hw *hal)
+{
+	AR5K_TRACE;
+	AR5K_REG_ENABLE_BITS(hal, AR5K_BEACON, AR5K_BEACON_RESET_TSF);
+}
+
+/*
+ * Initialize beacon timers
+ */
+void
+ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon,
+    u32 interval)
+{
+	u32 timer1, timer2, timer3;
+
+	AR5K_TRACE;
+	/*
+	 * Set the additional timers by mode
+	 */
+	switch (hal->ah_op_mode) {
+	case IEEE80211_IF_TYPE_STA:
+		if (hal->ah_version == AR5K_AR5210) {
+			timer1 = 0xffffffff;
+			timer2 = 0xffffffff;
+		} else {
+			timer1 = 0x0000ffff;
+			timer2 = 0x0007ffff;
+		}
+		break;
+
+	default:
+		timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) <<
+		    0x00000003;
+		timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) <<
+		    0x00000003;
+	}
+
+	timer3 = next_beacon +
+	    (hal->ah_atim_window ? hal->ah_atim_window : 1);
+
+	/*
+	 * Set the beacon register and enable all timers.
+	 * (next beacon, DMA beacon, software beacon, ATIM window time)
+	 */
+	ath5k_hw_reg_write(hal, next_beacon, AR5K_TIMER0);
+	ath5k_hw_reg_write(hal, timer1, AR5K_TIMER1);
+	ath5k_hw_reg_write(hal, timer2, AR5K_TIMER2);
+	ath5k_hw_reg_write(hal, timer3, AR5K_TIMER3);
+
+	ath5k_hw_reg_write(hal, interval & (AR5K_BEACON_PERIOD |
+			AR5K_BEACON_RESET_TSF | AR5K_BEACON_ENABLE),
+		AR5K_BEACON);
+}
+
+/*
+ * Set beacon timers
+ */
+void
+ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *state)
+{
+	u32 cfp_period, next_cfp, dtim, interval, next_beacon;
+
+ 	/* 
+	 * TODO: should be changed through *state
+	 * review struct ath5k_beacon_state struct
+	 *
+	 * XXX: These are used for cfp period bellow, are they
+	 * ok ? Is it O.K. for tsf here to be 0 or should we use
+	 * get_tsf ?
+	 */
+	u32 dtim_count = 0; /* XXX */
+	u32 cfp_count = 0; /* XXX */
+	u32 tsf = 0; /* XXX */
+
+	AR5K_TRACE;
+	/* Return on an invalid beacon state */
+	if (state->bs_interval < 1)
+		return;
+
+	interval = state->bs_interval;
+	dtim = state->bs_dtim_period;
+
+	/*
+	 * PCF support?
+	 */
+	if (state->bs_cfp_period > 0) {
+		/* 
+		 * Enable PCF mode and set the CFP 
+		 * (Contention Free Period) and timer registers
+		 */
+		cfp_period = state->bs_cfp_period * state->bs_dtim_period *
+		    state->bs_interval;
+		next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
+		    state->bs_interval;
+
+		AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1,
+				AR5K_STA_ID1_DEFAULT_ANTENNA |
+				AR5K_STA_ID1_PCF);
+		ath5k_hw_reg_write(hal, cfp_period, AR5K_CFP_PERIOD);
+		ath5k_hw_reg_write(hal, state->bs_cfp_max_duration, AR5K_CFP_DUR);
+		ath5k_hw_reg_write(hal, (tsf + (next_cfp == 0 ? cfp_period :
+						next_cfp)) << 3, AR5K_TIMER2);
+	} else {
+		/* Disable PCF mode */
+		AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1,
+				AR5K_STA_ID1_DEFAULT_ANTENNA |
+				AR5K_STA_ID1_PCF);
+	}
+
+	/*
+	 * Enable the beacon timer register
+	 */
+	ath5k_hw_reg_write(hal, state->bs_next_beacon, AR5K_TIMER0);
+
+	/*
+	 * Start the beacon timers
+	 */
+	ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_BEACON) &~
+		(AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) |
+		AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
+		AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,
+		AR5K_BEACON_PERIOD), AR5K_BEACON);
+
+	/*
+	 * Write new beacon miss threshold, if it appears to be valid
+	 * XXX: Figure out right values for min <= bs_bmiss_threshold <= max
+	 * and return if its not in range. We can test this by reading value and
+	 * setting value to a largest value and seeing which values register.
+	 */
+
+	AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR,
+	    AR5K_RSSI_THR_BMISS, state->bs_bmiss_threshold);
+
+	/*
+	 * Set sleep control register
+	 * XXX: Didn't find this in 5210 code but since this register
+	 * exists also in ar5k's 5210 headers i leave it as common code.
+	 */
+	AR5K_REG_WRITE_BITS(hal, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR,
+			(state->bs_sleep_duration - 3) << 3);
+
+	/*
+	 * Set enhanced sleep registers on 5212
+	 */
+	if (hal->ah_version == AR5K_AR5212) {
+		if ((state->bs_sleep_duration > state->bs_interval) &&
+		(roundup(state->bs_sleep_duration, interval) ==
+		state->bs_sleep_duration))
+			interval = state->bs_sleep_duration;
+
+		if (state->bs_sleep_duration > dtim &&
+		(dtim == 0 || roundup(state->bs_sleep_duration, dtim) ==
+		state->bs_sleep_duration))
+			dtim = state->bs_sleep_duration;
+
+		if (interval > dtim)
+			return;
+	
+		next_beacon = interval == dtim ?
+			state->bs_next_dtim: state->bs_next_beacon;
+
+		ath5k_hw_reg_write(hal,
+			AR5K_REG_SM((state->bs_next_dtim - 3) << 3,
+			AR5K_SLEEP0_NEXT_DTIM) |
+			AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) |
+			AR5K_SLEEP0_ENH_SLEEP_EN |
+			AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0);
+
+		ath5k_hw_reg_write(hal, AR5K_REG_SM((next_beacon - 3) << 3,
+			AR5K_SLEEP1_NEXT_TIM) |
+			AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1);
+
+		ath5k_hw_reg_write(hal,
+			AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) |
+			AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2);
+	}
+}
+
+/*
+ * Reset beacon timers
+ */
+void
+ath5k_hw_reset_beacon(struct ath_hw *hal)
+{
+	AR5K_TRACE;
+	/*
+	 * Disable beacon timer
+	 */
+	ath5k_hw_reg_write(hal, 0, AR5K_TIMER0);
+
+	/*
+	 * Disable some beacon register values
+	 */
+	AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1,
+				AR5K_STA_ID1_DEFAULT_ANTENNA | 
+				AR5K_STA_ID1_PCF);
+	ath5k_hw_reg_write(hal, AR5K_BEACON_PERIOD, AR5K_BEACON);
+}
+
+/*
+ * Wait for beacon queue to finish
+ * TODO: This function's name is misleading, rename
+ */
+bool
+ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr)
+{
+	bool ret;
+	int i;
+
+	AR5K_TRACE;
+
+	/* 5210 doesn't have QCU*/
+	if (hal->ah_version == AR5K_AR5210) {
+		/*
+		 * Wait for beaconn queue to finish by checking
+		 * Control Register and Beacon Status Register.
+		 */
+		for (i = (AR5K_TUNE_BEACON_INTERVAL / 2); i > 0 &&
+		(ath5k_hw_reg_read(hal, AR5K_BSR) & AR5K_BSR_TXQ1F) != 0 &&
+		(ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_CR_TXE1 ) != 0; i--);
+
+		/* Timeout... */
+		if (i <= 0) {
+			/*
+			 * Re-schedule the beacon queue
+			 */
+			ath5k_hw_reg_write(hal, phys_addr, AR5K_NOQCU_TXDP1);
+			ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, AR5K_BCR);
+
+			return false;
+		}
+		ret= true;
+
+	} else {
+	/*5211/5212*/
+		ret = ath5k_hw_register_timeout(hal,
+			AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON),
+			AR5K_QCU_STS_FRMPENDCNT, 0, false) ? false : true;
+
+		if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON))
+			return false;
+	}
+
+	return ret;
+}
+
+/*
+ * Update mib counters (statistics)
+ */
+void
+ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics)
+{
+	AR5K_TRACE;
+	/* Read-And-Clear */
+	statistics->ackrcv_bad += ath5k_hw_reg_read(hal, AR5K_ACK_FAIL);
+	statistics->rts_bad += ath5k_hw_reg_read(hal, AR5K_RTS_FAIL);
+	statistics->rts_good += ath5k_hw_reg_read(hal, AR5K_RTS_OK);
+	statistics->fcs_bad += ath5k_hw_reg_read(hal, AR5K_FCS_FAIL);
+	statistics->beacons += ath5k_hw_reg_read(hal, AR5K_BEACON_CNT);
+
+	/* Reset profile count registers on 5212*/
+	if (hal->ah_version == AR5K_AR5212) {
+		ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_TX);
+		ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_RX);
+		ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_RXCLR);
+		ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_CYCLE);
+	}
+}
+
+/*
+ * ACK/CTS Timeouts
+ */
+
+/*
+ * Set ACK timeout on PCU
+ */
+bool
+ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout)
+{
+	AR5K_TRACE;
+	if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK),
+	    hal->ah_turbo) <= timeout)
+		return false;
+
+	AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
+	    ath5k_hw_htoclock(timeout, hal->ah_turbo));
+
+	return true;
+}
+
+/*
+ * Read the ACK timeout from PCU
+ */
+unsigned int
+ath5k_hw_get_ack_timeout(struct ath_hw *hal)
+{
+	AR5K_TRACE;
+	return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TIME_OUT),
+	    AR5K_TIME_OUT_ACK), hal->ah_turbo));
+}
+
+/*
+ * Set CTS timeout on PCU
+ */
+bool
+ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout)
+{
+	AR5K_TRACE;
+	if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS),
+	    hal->ah_turbo) <= timeout)
+		return false;
+
+	AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
+	    ath5k_hw_htoclock(timeout, hal->ah_turbo));
+
+	return true;
+}
+
+/*
+ * Read CTS timeout from PCU
+ */
+unsigned int
+ath5k_hw_get_cts_timeout(struct ath_hw *hal)
+{
+	AR5K_TRACE;
+	return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TIME_OUT),
+	    AR5K_TIME_OUT_CTS), hal->ah_turbo));
+}
+
+/*
+ * Key table (WEP) functions
+ */
+
+int ath5k_hw_reset_key(struct ath_hw *hal, u16 entry)
+{
+	unsigned int i;
+
+	AR5K_TRACE;
+	AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
+
+	for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
+		ath5k_hw_reg_write(hal, 0, AR5K_KEYTABLE_OFF(entry, i));
+
+	/* Set NULL encryption on non-5210*/
+	if (hal->ah_version != AR5K_AR5210)
+		ath5k_hw_reg_write(hal, AR5K_KEYTABLE_TYPE_NULL,
+				AR5K_KEYTABLE_TYPE(entry));
+
+	return 0;
+}
+
+int ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry)
+{
+	AR5K_TRACE;
+	AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
+
+	/* Check the validation flag at the end of the entry */
+	return ath5k_hw_reg_read(hal, AR5K_KEYTABLE_MAC1(entry)) &
+		AR5K_KEYTABLE_VALID;
+}
+
+int ath5k_hw_set_key(struct ath_hw *hal, u16 entry,
+		const struct ieee80211_key_conf *key, const u8 *mac)
+{
+	unsigned int i;
+	u32 key_v[AR5K_KEYCACHE_SIZE - 2] = {};
+
+	AR5K_TRACE;
+	AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
+
+	switch (key->keylen) {
+	case 40 / 8:
+		memcpy(&key_v[0], key->key, 4);
+		memcpy(&key_v[1], key->key + 4, 1);
+		key_v[5] = AR5K_KEYTABLE_TYPE_40;
+		break;
+
+	case 104 / 8:
+		memcpy(&key_v[0], key->key, 4);
+		memcpy(&key_v[1], key->key + 4, 2);
+		memcpy(&key_v[2], key->key + 6, 4);
+		memcpy(&key_v[3], key->key + 10, 2);
+		memcpy(&key_v[4], key->key + 12, 1);
+		key_v[5] = AR5K_KEYTABLE_TYPE_104;
+		break;
+
+	case 128 / 8:
+		memcpy(&key_v[0], key->key, 4);
+		memcpy(&key_v[1], key->key + 4, 2);
+		memcpy(&key_v[2], key->key + 6, 4);
+		memcpy(&key_v[3], key->key + 10, 2);
+		memcpy(&key_v[4], key->key + 12, 4);
+		key_v[5] = AR5K_KEYTABLE_TYPE_128;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(key_v); i++)
+		ath5k_hw_reg_write(hal, key_v[i], AR5K_KEYTABLE_OFF(entry, i));
+
+	return ath5k_hw_set_key_lladdr(hal, entry, mac);
+}
+
+int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac)
+{
+	u32 low_id, high_id;
+
+	AR5K_TRACE;
+	 /* Invalid entry (key table overflow) */
+	AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
+
+	/* MAC may be NULL if it's a broadcast key. In this case no need to 
+ 	 * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */
+	if (unlikely(mac == NULL)) {
+		low_id = 0xffffffff;
+		high_id = 0xffff | AR5K_KEYTABLE_VALID;
+	} else {
+		low_id = AR5K_LOW_ID(mac);
+		high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID;
+	}
+
+	ath5k_hw_reg_write(hal, low_id, AR5K_KEYTABLE_MAC0(entry));
+	ath5k_hw_reg_write(hal, high_id, AR5K_KEYTABLE_MAC1(entry));
+
+	return 0;
+}
+
+
+/********************************************\
+Queue Control Unit, DFS Control Unit Functions
+\********************************************/
+
+/*
+ * Initialize a transmit queue
+ */
+int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type,
+		struct ath5k_txq_info *queue_info)
+{
+	unsigned int queue;
+	int ret;
+
+	AR5K_TRACE;
+
+	/*
+	 * Get queue by type
+	 */
+	/*5210 only has 2 queues*/
+	if (hal->ah_version == AR5K_AR5210) {
+		switch (queue_type) {
+			case AR5K_TX_QUEUE_DATA:
+				queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
+				break;
+			case AR5K_TX_QUEUE_BEACON:
+			case AR5K_TX_QUEUE_CAB:
+				queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
+				break;
+			default:
+				return -EINVAL;
+		}
+	} else {
+		switch (queue_type) {
+			case AR5K_TX_QUEUE_DATA:
+				for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
+					hal->ah_txq[queue].tqi_type != 
+					AR5K_TX_QUEUE_INACTIVE; queue++) {
+
+					if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
+						return -EINVAL;
+				}
+				break;
+			case AR5K_TX_QUEUE_UAPSD:
+				queue = AR5K_TX_QUEUE_ID_UAPSD;
+				break;
+			case AR5K_TX_QUEUE_BEACON:
+				queue = AR5K_TX_QUEUE_ID_BEACON;
+				break;
+			case AR5K_TX_QUEUE_CAB:
+				queue = AR5K_TX_QUEUE_ID_CAB;
+				break;
+			case AR5K_TX_QUEUE_XR_DATA:
+				if (hal->ah_version != AR5K_AR5212)
+					AR5K_PRINTF("XR data queues only "
+							"supported in 5212!");
+				queue = AR5K_TX_QUEUE_ID_XR_DATA;
+				break;
+			default:
+				return -EINVAL;
+		}	
+	}
+
+	/*
+	 * Setup internal queue structure
+	 */
+	memset(&hal->ah_txq[queue], 0, sizeof(struct ath5k_txq_info));
+	hal->ah_txq[queue].tqi_type = queue_type;
+
+	if (queue_info != NULL) {
+		queue_info->tqi_type = queue_type;
+		ret = ath5k_hw_setup_tx_queueprops(hal, queue, queue_info);
+		if (ret)
+			return ret;
+	}
+	/*
+	 * We use ah_txq_interrupts to hold a temp value for
+	 * the Secondary interrupt mask registers on 5211+
+	 * check out ath5k_hw_reset_tx_queue
+	 */
+	AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue);
+
+	return queue;
+}
+
+/*
+ * Setup a transmit queue
+ */
+int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue,
+				const struct ath5k_txq_info *queue_info)
+{
+	AR5K_TRACE;
+	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
+
+	if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) 
+		return -EIO;
+
+	memcpy(&hal->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info));
+
+	/*XXX: Is this supported on 5210 ?*/
+	if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && 
+			((queue_info->tqi_subtype == AR5K_WME_AC_VI) ||
+			(queue_info->tqi_subtype == AR5K_WME_AC_VO))) ||
+			queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD)
+		hal->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
+
+	return 0;
+}
+
+/*
+ * Get properties for a specific transmit queue
+ */
+bool
+ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info)
+{
+	AR5K_TRACE;
+	memcpy(queue_info, &hal->ah_txq[queue], sizeof(struct ath5k_txq_info));
+	return true;
+}
+
+/*
+ * Set a transmit queue inactive
+ */
+void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue)
+{
+	AR5K_TRACE;
+	if (queue >= hal->ah_capabilities.cap_queues.q_tx_num) {
+		WARN_ON(1);
+		return;
+	}
+
+	/* This queue will be skipped in further operations */
+	hal->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
+	/*For SIMR setup*/
+	AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue);
+}
+
+/*
+ * Set DFS params for a transmit queue
+ */
+bool
+ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
+{
+	u32 cw_min, cw_max, retry_lg, retry_sh;
+	struct ath5k_txq_info *tq = &hal->ah_txq[queue];
+	int i;
+	struct ath5k_ar5210_ini_mode ar5210_mode[] = 
+			AR5K_AR5210_INI_MODE(hal, hal->ah_aifs + tq->tqi_aifs);
+
+	AR5K_TRACE;
+	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
+
+	tq = &hal->ah_txq[queue];
+
+	if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
+		return true;
+
+	if (hal->ah_version == AR5K_AR5210) {
+		/* Only handle data queues, others will be ignored */
+		if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
+			return true;
+
+		/*
+		 * Write initial mode register settings
+		 */
+		for (i = 0; i < ARRAY_SIZE(ar5210_mode); i++)
+			ath5k_hw_reg_write(hal, hal->ah_turbo == true ?
+				ar5210_mode[i].mode_turbo :
+				ar5210_mode[i].mode_base,
+				(u32)ar5210_mode[i].mode_register);
+	}
+
+	/*
+	 * Calculate cwmin/max by channel mode
+	 */
+	cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN;
+	cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX;
+	hal->ah_aifs = AR5K_TUNE_AIFS;
+	/*XR is only supported on 5212*/
+	if (IS_CHAN_XR(hal->ah_current_channel)
+			&& (hal->ah_version == AR5K_AR5212)) {
+		cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_XR;
+		cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR;
+		hal->ah_aifs = AR5K_TUNE_AIFS_XR;
+	/*B mode is not supported on 5210*/
+	} else if (IS_CHAN_B(hal->ah_current_channel)
+			&& (hal->ah_version != AR5K_AR5210)) {
+		cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_11B;
+		cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B;
+		hal->ah_aifs = AR5K_TUNE_AIFS_11B;
+	}
+
+	cw_min = 1;
+	while (cw_min < hal->ah_cw_min)
+		cw_min = (cw_min << 1) | 1;
+
+	cw_min = tq->tqi_cw_min < 0 ?
+	    (cw_min >> (-tq->tqi_cw_min)) :
+	    ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
+	cw_max = tq->tqi_cw_max < 0 ?
+	    (cw_max >> (-tq->tqi_cw_max)) :
+	    ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
+
+	/*
+	 * Calculate and set retry limits
+	 */
+	if (hal->ah_software_retry == true) {
+		/* XXX Need to test this */
+		retry_lg = hal->ah_limit_tx_retries;
+		retry_sh = retry_lg =
+		    retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
+		    AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
+	} else {
+		retry_lg = AR5K_INIT_LG_RETRY;
+		retry_sh = AR5K_INIT_SH_RETRY;
+	}
+
+	/*No QCU/DCU [5210]*/
+	if (hal->ah_version == AR5K_AR5210) {
+		ath5k_hw_reg_write(hal,
+			(cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
+			| AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
+				AR5K_NODCU_RETRY_LMT_SLG_RETRY)
+			| AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
+				AR5K_NODCU_RETRY_LMT_SSH_RETRY)
+			| AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY)
+			| AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY),
+			AR5K_NODCU_RETRY_LMT);
+	} else {
+		/*QCU/DCU [5211+]*/
+		ath5k_hw_reg_write(hal,
+			AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
+				AR5K_DCU_RETRY_LMT_SLG_RETRY) |
+			AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
+				AR5K_DCU_RETRY_LMT_SSH_RETRY) |
+			AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) |
+			AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY),
+			AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
+
+	/*===Rest is also for QCU/DCU only [5211+]===*/
+
+		/*
+		 * Set initial content window (cw_min/cw_max)
+		 * and arbitrated interframe space (aifs)...
+		 */
+		ath5k_hw_reg_write(hal,
+			AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
+			AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
+			AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs,
+			AR5K_DCU_LCL_IFS_AIFS), AR5K_QUEUE_DFS_LOCAL_IFS(queue));
+
+		/*
+		 * Set misc registers
+		 */
+		ath5k_hw_reg_write(hal, AR5K_QCU_MISC_DCU_EARLY,
+			AR5K_QUEUE_MISC(queue));
+
+		if (tq->tqi_cbr_period) {
+			ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_cbr_period,
+				AR5K_QCU_CBRCFG_INTVAL) |
+				AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
+				AR5K_QCU_CBRCFG_ORN_THRES),
+				AR5K_QUEUE_CBRCFG(queue));
+			AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue),
+				AR5K_QCU_MISC_FRSHED_CBR);
+			if (tq->tqi_cbr_overflow_limit)
+				AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue),
+					AR5K_QCU_MISC_CBR_THRES_ENABLE);
+		}
+
+		if (tq->tqi_ready_time) {
+			ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_ready_time,
+				AR5K_QCU_RDYTIMECFG_INTVAL) |
+				AR5K_QCU_RDYTIMECFG_ENABLE,
+				AR5K_QUEUE_RDYTIMECFG(queue));
+		}
+
+		if (tq->tqi_burst_time) {
+			ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_burst_time,
+				AR5K_DCU_CHAN_TIME_DUR) |
+				AR5K_DCU_CHAN_TIME_ENABLE,
+				AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
+
+			if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) {
+				AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue),
+					AR5K_QCU_MISC_TXE);
+			}
+		}
+
+		if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) {
+			ath5k_hw_reg_write(hal, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
+				AR5K_QUEUE_DFS_MISC(queue));
+		}
+
+		if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
+			ath5k_hw_reg_write(hal, AR5K_DCU_MISC_BACKOFF_FRAG,
+				AR5K_QUEUE_DFS_MISC(queue));
+		}
+
+		/*
+		 * Set registers by queue type
+		 */
+		switch (tq->tqi_type) {
+			case AR5K_TX_QUEUE_BEACON:
+				AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue),
+					AR5K_QCU_MISC_FRSHED_DBA_GT |
+					AR5K_QCU_MISC_CBREXP_BCN |
+					AR5K_QCU_MISC_BCN_ENABLE);
+
+				AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_DFS_MISC(queue),
+					(AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
+					AR5K_DCU_MISC_ARBLOCK_CTL_S) |
+					AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
+					AR5K_DCU_MISC_BCN_ENABLE);
+
+				ath5k_hw_reg_write(hal,
+					((AR5K_TUNE_BEACON_INTERVAL -
+					(AR5K_TUNE_SW_BEACON_RESP - 
+					AR5K_TUNE_DMA_BEACON_RESP) -
+					AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
+					AR5K_QCU_RDYTIMECFG_ENABLE,
+					AR5K_QUEUE_RDYTIMECFG(queue));
+				break;
+
+		case AR5K_TX_QUEUE_CAB:
+			AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue),
+				AR5K_QCU_MISC_FRSHED_DBA_GT |
+				AR5K_QCU_MISC_CBREXP |
+				AR5K_QCU_MISC_CBREXP_BCN);
+
+			AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_DFS_MISC(queue),
+				(AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
+				AR5K_DCU_MISC_ARBLOCK_CTL_S));
+			break;
+
+		case AR5K_TX_QUEUE_UAPSD:
+			AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue),
+				AR5K_QCU_MISC_CBREXP);
+			break;
+
+		case AR5K_TX_QUEUE_DATA:
+		default:
+			break;
+		}
+
+		/*
+		 * Enable tx queue in the secondary interrupt mask registers
+		 */
+		ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts,
+			AR5K_SIMR0_QCU_TXOK) |
+			AR5K_REG_SM(hal->ah_txq_interrupts,
+				AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
+		ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts,
+			AR5K_SIMR1_QCU_TXERR), AR5K_SIMR1);
+		ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts,
+			AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2);
+	}	
+
+	return true;
+}
+
+/*
+ * Get number of pending frames
+ * for a specific queue [5211+]
+ */
+u32
+ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue) {
+	AR5K_TRACE;
+	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
+
+	/* Return if queue is declared inactive */
+	if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
+		return false;
+
+	/* XXX: How about AR5K_CFG_TXCNT ? */
+	if (hal->ah_version == AR5K_AR5210)
+		return false;
+
+	return AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT;
+}
+
+/*
+ * Set slot time
+ */
+bool
+ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time)
+{
+	AR5K_TRACE;
+	if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX)
+		return false;
+
+	if (hal->ah_version == AR5K_AR5210)
+		ath5k_hw_reg_write(hal, ath5k_hw_htoclock(slot_time,
+				hal->ah_turbo), AR5K_SLOT_TIME);
+	else
+		ath5k_hw_reg_write(hal, slot_time, AR5K_DCU_GBL_IFS_SLOT);
+
+	return true;
+}
+
+/*
+ * Get slot time
+ */
+unsigned int
+ath5k_hw_get_slot_time(struct ath_hw *hal)
+{
+	AR5K_TRACE;
+	if (hal->ah_version == AR5K_AR5210)
+		return (ath5k_hw_clocktoh(ath5k_hw_reg_read(hal, AR5K_SLOT_TIME) &
+		    0xffff, hal->ah_turbo));
+	else
+		return ath5k_hw_reg_read(hal, AR5K_DCU_GBL_IFS_SLOT) & 0xffff;
+}
+
+
+/******************************\
+ Hardware Descriptor Functions
+\******************************/
+
+/*
+ * TX Descriptor
+ */
+
+/*
+ * Initialize the 2-word tx descriptor on 5210/5211
+ */
+static int
+ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc,
+	unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type,
+	unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
+	unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
+	unsigned int rtscts_rate, unsigned int rtscts_duration)
+{
+	u32 frame_type;
+	struct ath5k_hw_2w_tx_desc *tx_desc;
+
+	tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0;
+
+	if (tx_tries0 == 0)
+		return -EINVAL;
+
+	/* Initialize control descriptor */
+	tx_desc->tx_control_0 = 0;
+	tx_desc->tx_control_1 = 0;
+
+	/* Setup control descriptor */
+
+	/*Verify packet length*/
+	tx_desc->tx_control_0 = pkt_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
+	if (tx_desc->tx_control_0 != pkt_len)
+		return -EINVAL;
+	/*
+	 * Verify header length
+	 * XXX: I only found that on 5210 code, does it work on 5211 ?
+	 */
+	if (hal->ah_version == AR5K_AR5210) {
+		tx_desc->tx_control_0 = hdr_len & AR5K_2W_TX_DESC_CTL0_HEADER_LEN;
+		if (tx_desc->tx_control_0 != hdr_len)
+			return -EINVAL;
+	}
+
+	/*Diferences between 5210-5211*/
+	if (hal->ah_version == AR5K_AR5210) {
+		switch (type) {
+			case AR5K_PKT_TYPE_BEACON:
+			case AR5K_PKT_TYPE_PROBE_RESP:
+				frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
+			case AR5K_PKT_TYPE_PIFS:
+				frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
+			default:
+				frame_type = type /*<< 2 ?*/;
+		}
+
+		tx_desc->tx_control_0 =
+			AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE)|
+			AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
+	} else {
+		tx_desc->tx_control_0 |=
+			AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
+			AR5K_REG_SM(antenna_mode, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
+		tx_desc->tx_control_1 =
+			AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
+	}
+#define _TX_FLAGS(_c, _flag)						\
+	if (flags & AR5K_TXDESC_##_flag)				\
+		tx_desc->tx_control_##_c |=				\
+			AR5K_2W_TX_DESC_CTL##_c##_##_flag
+
+	_TX_FLAGS(0, CLRDMASK);
+	_TX_FLAGS(0, VEOL);
+	_TX_FLAGS(0, INTREQ);
+	_TX_FLAGS(0, RTSENA);
+	_TX_FLAGS(1, NOACK);
+
+#undef _TX_FLAGS
+
+	/*
+	 * WEP crap
+	 */
+	if (key_index != AR5K_TXKEYIX_INVALID) {
+		tx_desc->tx_control_0 |=
+			AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
+		tx_desc->tx_control_1 |=
+			AR5K_REG_SM(key_index,
+			AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
+	}
+
+	/*
+	 * RTS/CTS Duration [5210 ?]
+	 */
+	if ((hal->ah_version == AR5K_AR5210) &&
+			(flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA))) {
+		tx_desc->tx_control_1 |=
+			rtscts_duration & AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
+	}
+
+	return 0;
+}
+
+/*
+ * Initialize the 4-word tx descriptor on 5212
+ */
+static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal,
+	struct ath_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
+	enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
+	unsigned int tx_tries0, unsigned int key_index,
+	unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate,
+	unsigned int rtscts_duration)
+{
+	struct ath5k_hw_4w_tx_desc *tx_desc;
+
+	AR5K_TRACE;
+
+	tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0;
+
+	/*
+	 * Validate input
+	 */
+	if (tx_tries0 == 0)
+		return -EINVAL;
+
+	/* Initialize status descriptor */
+	tx_desc->tx_control_0 = 0;
+	tx_desc->tx_control_1 = 0;
+	tx_desc->tx_control_2 = 0;
+	tx_desc->tx_control_3 = 0;
+
+	/* Setup status descriptor */
+	tx_desc->tx_control_0 = pkt_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
+	if (tx_desc->tx_control_0 != pkt_len)
+		return -EINVAL;
+
+	tx_desc->tx_control_0 |=
+		AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
+		AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
+	tx_desc->tx_control_1 = AR5K_REG_SM(type,
+					AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
+	tx_desc->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
+					AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
+	tx_desc->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
+
+#define _TX_FLAGS(_c, _flag)			\
+	if (flags & AR5K_TXDESC_##_flag)	\
+		tx_desc->tx_control_##_c |=	\
+			AR5K_4W_TX_DESC_CTL##_c##_##_flag
+
+	_TX_FLAGS(0, CLRDMASK);
+	_TX_FLAGS(0, VEOL);
+	_TX_FLAGS(0, INTREQ);
+	_TX_FLAGS(0, RTSENA);
+	_TX_FLAGS(0, CTSENA);
+	_TX_FLAGS(1, NOACK);
+
+#undef _TX_FLAGS
+
+	/*
+	 * WEP crap
+	 */
+	if (key_index != AR5K_TXKEYIX_INVALID) {
+		tx_desc->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
+		tx_desc->tx_control_1 |= AR5K_REG_SM(key_index,
+				AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
+	}
+
+	/*
+	 * RTS/CTS
+	 */
+	if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
+		if ((flags & AR5K_TXDESC_RTSENA) &&(flags & AR5K_TXDESC_CTSENA))
+			return -EINVAL;
+		tx_desc->tx_control_2 |= rtscts_duration &
+				AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
+		tx_desc->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
+				AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
+	}
+
+	return 0;
+}
+
+/*
+ * Initialize a 4-word XR tx descriptor on 5212
+ */
+static bool
+ath5k_hw_setup_xr_tx_desc(struct ath_hw *hal, struct ath_desc *desc,
+    unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
+    unsigned int tx_rate3, u_int tx_tries3)
+{
+	struct ath5k_hw_4w_tx_desc *tx_desc;
+
+	if (hal->ah_version == AR5K_AR5212) {
+		tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0;
+
+#define _XTX_TRIES(_n)							\
+	if (tx_tries##_n) {						\
+		tx_desc->tx_control_2 |=				\
+		    AR5K_REG_SM(tx_tries##_n,				\
+		    AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n);		\
+		tx_desc->tx_control_3 |=				\
+		    AR5K_REG_SM(tx_rate##_n,				\
+		    AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n);		\
+	}
+
+		_XTX_TRIES(1);
+		_XTX_TRIES(2);
+		_XTX_TRIES(3);
+
+#undef _XTX_TRIES
+
+		return true;
+	}
+
+	return(false);
+}
+
+/*
+ * Fill the 2-word tx descriptor on 5210/5211
+ */
+static int ath5k_hw_fill_2word_tx_desc(struct ath_hw *hal,
+	struct ath_desc *desc, unsigned int segment_length,
+	bool first_segment, bool last_segment)
+{
+	struct ath5k_hw_2w_tx_desc *tx_desc;
+
+	tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0;
+
+	/* Clear status descriptor */
+	memset(desc->ds_hw, 0, sizeof(desc->ds_hw));
+
+	/* Validate segment length and initialize the descriptor */
+	tx_desc->tx_control_1 = segment_length & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
+	if (tx_desc->tx_control_1 != segment_length)
+		return -EINVAL;
+
+	if (first_segment != true)
+		tx_desc->tx_control_0 &= ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
+
+	if (last_segment != true)
+		tx_desc->tx_control_1 |= AR5K_2W_TX_DESC_CTL1_MORE;
+
+	return 0;
+}
+
+/*
+ * Fill the 4-word tx descriptor on 5212
+ * XXX: Added an argument *last_desc -need revision
+ */
+static int ath5k_hw_fill_4word_tx_desc(struct ath_hw *hal,
+	struct ath_desc *desc, unsigned int segment_length,
+	bool first_segment, bool last_segment)
+{
+	struct ath5k_hw_4w_tx_desc *tx_desc;
+	struct ath5k_hw_tx_status *tx_status;
+
+	AR5K_TRACE;
+	tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0;
+	tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2];
+
+	/* Clear status descriptor */
+	memset(tx_status, 0, sizeof(struct ath5k_hw_tx_status));
+
+	/* Validate segment length and initialize the descriptor */
+	tx_desc->tx_control_1 = segment_length & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
+	if (tx_desc->tx_control_1 != segment_length)
+		return -EINVAL;
+
+	if (first_segment != true)
+		tx_desc->tx_control_0 &= ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
+
+	if (last_segment != true)
+		tx_desc->tx_control_1 |= AR5K_4W_TX_DESC_CTL1_MORE;
+
+	return 0;
+}
+
+/*
+ * Proccess the tx status descriptor on 5210/5211
+ */
+static int ath5k_hw_proc_2word_tx_status(struct ath_hw *hal,
+		struct ath_desc *desc)
+{
+	struct ath5k_hw_tx_status *tx_status;
+	struct ath5k_hw_2w_tx_desc *tx_desc;
+
+	tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0;
+	tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[0];
+
+	/* No frame has been send or error */
+	if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)
+		return -EINPROGRESS;
+
+	/*
+	 * Get descriptor status
+	 */
+	desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
+		AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
+	desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
+		AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
+	desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
+		AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
+	/*TODO: desc->ds_us.tx.ts_virtcol + test*/
+	desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
+		AR5K_DESC_TX_STATUS1_SEQ_NUM);
+	desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
+		AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
+	desc->ds_us.tx.ts_antenna = 1;
+	desc->ds_us.tx.ts_status = 0;
+	desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_0,
+		AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
+
+	if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
+		if (tx_status->tx_status_0 &
+				AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
+			desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY;
+
+		if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
+			desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO;
+
+		if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
+			desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT;
+	}
+
+	return 0;
+}
+
+/*
+ * Proccess a tx descriptor on 5212
+ */
+static int ath5k_hw_proc_4word_tx_status(struct ath_hw *hal,
+		struct ath_desc *desc)
+{
+	struct ath5k_hw_tx_status *tx_status;
+	struct ath5k_hw_4w_tx_desc *tx_desc;
+
+	AR5K_TRACE;
+	tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0;
+	tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2];
+
+	/* No frame has been send or error */
+	if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)
+		return -EINPROGRESS;
+
+	/*
+	 * Get descriptor status
+	 */
+	desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
+		AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
+	desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
+		AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
+	desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
+		AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
+	desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
+		AR5K_DESC_TX_STATUS1_SEQ_NUM);
+	desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
+		AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
+	desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 &
+		AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
+	desc->ds_us.tx.ts_status = 0;
+
+	switch (AR5K_REG_MS(tx_status->tx_status_1,
+			AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) {
+	case 0:
+		desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 &
+			AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
+		break;
+	case 1:
+		desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3,
+			AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
+		desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2,
+			AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
+		break;
+	case 2:
+		desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3,
+			AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
+		desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2,
+			AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
+		break;
+	case 3:
+		desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3,
+			AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
+		desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2,
+			AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3);
+		break;
+	}
+
+	if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
+		if (tx_status->tx_status_0 &
+				AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
+			desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY;
+
+		if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
+			desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO;
+
+		if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
+			desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT;
+	}
+
+	return 0;
+}
+
+/*
+ * RX Descriptor
+ */
+
+/*
+ * Initialize an rx descriptor
+ */
+int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc,
+			u32 size, unsigned int flags)
+{
+	struct ath5k_rx_desc *rx_desc;
+
+	AR5K_TRACE;
+	rx_desc = (struct ath5k_rx_desc*)&desc->ds_ctl0;
+
+	/*
+	 *Clear ds_hw 
+	 * If we don't clean the status descriptor,
+	 * while scanning we get too many results, 
+	 * most of them virtual, after some secs 
+	 * of scanning system hangs. M.F.
+	*/
+	memset(desc->ds_hw, 0, sizeof(desc->ds_hw));
+
+	/*Initialize rx descriptor*/
+	rx_desc->rx_control_0 = 0;
+	rx_desc->rx_control_1 = 0;
+
+	/* Setup descriptor */
+	rx_desc->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
+	if (rx_desc->rx_control_1 != size)
+		return -EINVAL;
+
+	if (flags & AR5K_RXDESC_INTREQ)
+		rx_desc->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
+
+	return 0;
+}
+
+/*
+ * Proccess the rx status descriptor on 5210/5211
+ */
+static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal,
+		struct ath_desc *desc)
+{
+	struct ath5k_hw_old_rx_status *rx_status;
+
+	rx_status = (struct ath5k_hw_old_rx_status*)&desc->ds_hw[0];
+
+	/* No frame received / not ready */
+	if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE) == 0)
+		return -EINPROGRESS;
+
+	/*
+	 * Frame receive status
+	 */
+	desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
+	    AR5K_OLD_RX_DESC_STATUS0_DATA_LEN;
+	desc->ds_us.rx.rs_rssi =
+	    AR5K_REG_MS(rx_status->rx_status_0,
+	    	AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL);
+	desc->ds_us.rx.rs_rate =
+	    AR5K_REG_MS(rx_status->rx_status_0,
+	    	AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE);
+	desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
+	    AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA;
+	desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
+	    AR5K_OLD_RX_DESC_STATUS0_MORE;
+	desc->ds_us.rx.rs_tstamp =
+	    AR5K_REG_MS(rx_status->rx_status_1,
+	    	AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
+	desc->ds_us.rx.rs_status = 0;
+
+	/*
+	 * Key table status
+	 */
+	if (rx_status->rx_status_1 &
+	    AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID)
+		desc->ds_us.rx.rs_keyix =
+		    AR5K_REG_MS(rx_status->rx_status_1,
+		    	AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX);
+	else
+		desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID;
+
+	/*
+	 * Receive/descriptor errors
+	 */
+	if ((rx_status->rx_status_1 &
+	AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
+		if (rx_status->rx_status_1 &
+				AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR)
+			desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC;
+
+		if (rx_status->rx_status_1 &
+				AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN)
+			desc->ds_us.rx.rs_status |= AR5K_RXERR_FIFO;
+
+		if (rx_status->rx_status_1 &
+				AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR) {
+			desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY;
+			desc->ds_us.rx.rs_phyerr =
+				AR5K_REG_MS(rx_status->rx_status_1,
+					AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR);
+		}
+
+		if (rx_status->rx_status_1 &
+				AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
+			desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT;
+	}
+
+	return 0;
+}
+
+/*
+ * Proccess the rx status descriptor on 5212
+ */
+static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal,
+		struct ath_desc *desc)
+{
+	struct ath5k_hw_new_rx_status *rx_status;
+	struct ath5k_hw_rx_error *rx_err;
+
+	AR5K_TRACE;
+	rx_status = (struct ath5k_hw_new_rx_status*)&desc->ds_hw[0];
+
+	/* Overlay on error */
+	rx_err = (struct ath5k_hw_rx_error*)&desc->ds_hw[0];
+
+	/* No frame received / not ready */
+	if ((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE) == 0)
+		return -EINPROGRESS;
+
+	/*
+	 * Frame receive status
+	 */
+	desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
+		AR5K_NEW_RX_DESC_STATUS0_DATA_LEN;
+	desc->ds_us.rx.rs_rssi =
+		AR5K_REG_MS(rx_status->rx_status_0,
+			AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL);
+	desc->ds_us.rx.rs_rate =
+		AR5K_REG_MS(rx_status->rx_status_0,
+			AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE);
+	desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
+		AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA;
+	desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
+		AR5K_NEW_RX_DESC_STATUS0_MORE;
+	desc->ds_us.rx.rs_tstamp =
+		AR5K_REG_MS(rx_status->rx_status_1,
+			AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
+	desc->ds_us.rx.rs_status = 0;
+
+	/*
+	 * Key table status
+	 */
+	if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID)
+		desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
+				AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX);
+	else
+		desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID;
+
+	/*
+	 * Receive/descriptor errors
+	 */
+	if ((rx_status->rx_status_1 &
+			AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
+		if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR)
+			desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC;
+
+		if (rx_status->rx_status_1 &AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR){
+			desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY;
+			desc->ds_us.rx.rs_phyerr =
+				AR5K_REG_MS(rx_err->rx_error_1,
+					AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
+		}
+
+		if (rx_status->rx_status_1 &
+				AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
+			desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT;
+
+		if (rx_status->rx_status_1 &
+				AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR)
+			desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC;
+	}
+
+	return 0;
+}
+
+
+
+
+/****************\
+  GPIO Functions
+\****************/
+
+/*
+ * Set led state
+ */
+void
+ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state)
+{
+	u32 led;
+	/*5210 has different led mode handling*/
+	u32 led_5210;
+
+	AR5K_TRACE;
+
+	/*Reset led status*/
+	if (hal->ah_version != AR5K_AR5210)
+		AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG,
+			AR5K_PCICFG_LEDMODE |  AR5K_PCICFG_LED);
+	else
+		AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG,
+				AR5K_PCICFG_LED);
+
+	/*
+	 * Some blinking values, define at your wish
+	 */
+	switch (state) {
+	case AR5K_LED_SCAN:
+	case AR5K_LED_AUTH:
+		led = AR5K_PCICFG_LEDMODE_PROP |
+			AR5K_PCICFG_LED_PEND;
+		led_5210 = AR5K_PCICFG_LED_PEND|
+			AR5K_PCICFG_LED_BCTL;
+		break;
+
+	case AR5K_LED_INIT:
+		led = AR5K_PCICFG_LEDMODE_PROP |
+			AR5K_PCICFG_LED_NONE;
+		led_5210 = AR5K_PCICFG_LED_PEND;
+		break;
+
+	case AR5K_LED_ASSOC:
+	case AR5K_LED_RUN:
+		led = AR5K_PCICFG_LEDMODE_PROP |
+			AR5K_PCICFG_LED_ASSOC;
+		led_5210 = AR5K_PCICFG_LED_ASSOC;
+		break;
+
+	default:
+		led = AR5K_PCICFG_LEDMODE_PROM |
+			AR5K_PCICFG_LED_NONE;
+		led_5210 = AR5K_PCICFG_LED_PEND;
+		break;
+	}
+
+	/*Write new status to the register*/
+	if (hal->ah_version != AR5K_AR5210)
+		AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, led);
+	else
+		AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, led_5210);
+}
+
+/*
+ * Set GPIO outputs
+ */
+bool
+ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio)
+{
+	AR5K_TRACE;
+	if (gpio > AR5K_NUM_GPIO)
+		return false;
+
+	ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_GPIOCR) &~
+		AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR);
+
+	return true;
+}
+
+/*
+ * Set GPIO inputs
+ */
+bool
+ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio)
+{
+	AR5K_TRACE;
+	if (gpio > AR5K_NUM_GPIO)
+		return false;
+
+	ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_GPIOCR) &~
+		AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR);
+
+	return true;
+}
+
+/*
+ * Get GPIO state
+ */
+u32
+ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio)
+{
+	AR5K_TRACE;
+	if (gpio > AR5K_NUM_GPIO)
+		return 0xffffffff;
+
+	/* GPIO input magic */
+	return (((ath5k_hw_reg_read(hal, AR5K_GPIODI) &
+	    AR5K_GPIODI_M) >> gpio) & 0x1);
+}
+
+/*
+ * Set GPIO state
+ */
+bool
+ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val)
+{
+	u32 data;
+	AR5K_TRACE;
+
+	if (gpio > AR5K_NUM_GPIO)
+		return false;
+
+	/* GPIO output magic */
+	data =  ath5k_hw_reg_read(hal, AR5K_GPIODO);
+
+	data &= ~(1 << gpio);
+	data |= (val&1) << gpio;
+
+	ath5k_hw_reg_write(hal, data, AR5K_GPIODO);
+
+	return true;
+}
+
+/*
+ * Initialize the GPIO interrupt (RFKill switch)
+ */
+void
+ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio,
+    u32 interrupt_level)
+{
+	u32 data;
+
+	AR5K_TRACE;
+	if (gpio > AR5K_NUM_GPIO)
+		return;
+
+	/*
+	 * Set the GPIO interrupt
+	 */
+	data = (ath5k_hw_reg_read(hal, AR5K_GPIOCR) &
+	    ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH |
+	    AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) |
+	    (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA);
+
+	ath5k_hw_reg_write(hal, interrupt_level ? data :
+		(data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR);
+
+	hal->ah_imr |= AR5K_IMR_GPIO;
+
+	/* Enable GPIO interrupts */
+	AR5K_REG_ENABLE_BITS(hal, AR5K_PIMR, AR5K_IMR_GPIO);
+}
+
+
+
+
+/*********************************\
+ Regulatory Domain/Channels Setup
+\*********************************/
+
+/*
+ * Following 2 functions come from net80211 
+ * TODO: These do not belong here, they have nothing
+ * to do with hw. I left them here temporarily for
+ * combatibility.
+ * M.F.
+ */
+
+/*
+ * Convert MHz frequency to IEEE channel number.
+ */
+unsigned int
+ath_hal_mhz2ieee(unsigned int freq, u_int flags)
+{
+	if (flags & CHANNEL_2GHZ) {	/* 2GHz band */
+		if (freq == 2484)		/* Japan */
+			return 14;
+		/* don't number non-IEEE channels unless we do channel tests */
+		if ((freq >= 2412) && (freq < 2484))
+			return (freq - 2407) / 5;
+		if (CHAN_DEBUG == 1) /* 15-26 */
+			return ((freq - 2512)/20) + 15;
+		return 0;
+	} else if (flags & CHANNEL_5GHZ)	{	/* 5Ghz band */
+		/* don't number non-IEEE channels unless we do channel tests */
+		if (((freq >= 5150) && (freq <= 5825))|| CHAN_DEBUG == 1)
+			return (freq - 5000) / 5;
+		return 0;
+	} else
+		/* something is fishy, don't do anything */
+		return 0;
+}
+
+/*
+ * Check if a channel is supported
+ */
+bool
+ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags)
+{
+	/* Check if the channel is in our supported range */
+	if (flags & CHANNEL_2GHZ) {
+		if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) &&
+		    (freq <= hal->ah_capabilities.cap_range.range_2ghz_max))
+			return true;
+	} else if (flags & CHANNEL_5GHZ) 
+		if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) &&
+		    (freq <= hal->ah_capabilities.cap_range.range_5ghz_max))
+			return true;
+
+	return false;
+}
+
+u16
+ath5k_get_regdomain(struct ath_hw *hal)
+{
+	u16 regdomain;
+	enum ieee80211_regdomain ieee_regdomain;
+#ifdef COUNTRYCODE
+	u16 code;
+#endif
+
+	ath5k_eeprom_regulation_domain(hal, false, &ieee_regdomain);
+	hal->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain;
+
+#ifdef COUNTRYCODE
+	/*
+	 * Get the regulation domain by country code. This will ignore
+	 * the settings found in the EEPROM.
+	 */
+	code = ieee80211_name2countrycode(COUNTRYCODE);
+	ieee_regdomain = ieee80211_countrycode2regdomain(code);
+#endif
+
+	regdomain = ath5k_regdomain_from_ieee(ieee_regdomain);
+	hal->ah_capabilities.cap_regdomain.reg_current = regdomain;
+
+	return regdomain;
+}
+
+/*************************\
+  PHY/RF access functions
+\*************************/
+
+/*
+ * Set a channel on the radio chip
+ */
+bool
+ath5k_hw_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
+{
+	bool ret;
+
+	/*
+	 * Check bounds supported by the PHY
+	 * (don't care about regulation restrictions at this point)
+	 */
+	if ((channel->freq < hal->ah_capabilities.cap_range.range_2ghz_min ||
+	    channel->freq > hal->ah_capabilities.cap_range.range_2ghz_max) &&
+	    (channel->freq < hal->ah_capabilities.cap_range.range_5ghz_min ||
+	    channel->freq > hal->ah_capabilities.cap_range.range_5ghz_max)) {
+		AR5K_PRINTF("channel out of supported range (%u MHz)\n",
+		    channel->freq);
+		return false;
+	}
+
+	/*
+	 * Set the channel and wait
+	 */
+	if (hal->ah_radio == AR5K_RF5110)
+		ret = ath5k_hw_rf5110_channel(hal, channel);
+	else if (hal->ah_radio == AR5K_RF5111)
+		ret = ath5k_hw_rf5111_channel(hal, channel);
+	else
+		ret = ath5k_hw_rf5112_channel(hal, channel);
+
+	if (ret == false)
+		return ret;
+
+	hal->ah_current_channel.freq = channel->freq;
+	hal->ah_current_channel.val = channel->val;
+	hal->ah_turbo = channel->val == CHANNEL_T ? true : false;
+
+	return true;
+}
+
+/*
+ * Convertion needed for RF5110
+ */
+u32
+ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
+{
+	u32 athchan;
+
+	/*
+	 * Convert IEEE channel/MHz to an internal channel value used
+	 * by the AR5210 chipset. This has not been verified with
+	 * newer chipsets like the AR5212A who have a completely
+	 * different RF/PHY part.
+	 */
+	athchan = (ath5k_hw_bitswap((ath_hal_mhz2ieee(channel->freq,
+	    channel->val) - 24) / 2, 5) << 1) |
+	    (1 << 6) | 0x1;
+
+	return athchan;
+}
+
+/*
+ * Set channel on RF5110
+ */
+bool
+ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
+{
+	u32 data;
+
+	/*
+	 * Set the channel and wait
+	 */
+	data = ath5k_hw_rf5110_chan2athchan(channel);
+	AR5K_PHY_WRITE(hal, 0x27, data);
+	AR5K_PHY_WRITE(hal, 0x30, 0);
+	mdelay(1);
+
+	return true;
+}
+
+/*
+ * Convertion needed for 5111
+ */
+bool
+ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athchan)
+{
+	int channel;
+
+	/* Cast this value to catch negative channel numbers (>= -19) */ 
+	channel = (int)ieee;
+
+	/*
+	 * Map 2GHz IEEE channel to 5GHz Atheros channel
+	 */
+	if (channel <= 13) {
+		athchan->a2_athchan = 115 + channel;
+		athchan->a2_flags = 0x46;
+	} else if (channel == 14) {
+		athchan->a2_athchan = 124;
+		athchan->a2_flags = 0x44;
+	} else if (channel >= 15 && channel <= 26) {
+		athchan->a2_athchan = ((channel - 14) * 4) + 132;
+		athchan->a2_flags = 0x46;
+	} else
+		return false;
+
+	return true;
+}
+
+/*
+ * Set channel on 5111
+ */
+bool
+ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
+{
+	unsigned int ieee_channel, ath_channel;
+	u32 data0, data1, clock;
+	struct ath5k_athchan_2ghz ath_channel_2ghz;
+
+	/*
+	 * Set the channel on the RF5111 radio
+	 */
+	data0 = data1 = 0;
+	ath_channel = ieee_channel = ath_hal_mhz2ieee(channel->freq,
+	    channel->val);
+
+	if (channel->val & CHANNEL_2GHZ) {
+		/* Map 2GHz channel to 5GHz Atheros channel ID */
+		if (ath5k_hw_rf5111_chan2athchan(ieee_channel,
+			&ath_channel_2ghz) == false)
+			return false;
+
+		ath_channel = ath_channel_2ghz.a2_athchan;
+		data0 = ((ath5k_hw_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff)
+		    << 5) | (1 << 4);
+	}
+
+	if (ath_channel < 145 || !(ath_channel & 1)) {
+		clock = 1;
+		data1 = ((ath5k_hw_bitswap(ath_channel - 24, 8) & 0xff) << 2)
+		    | (clock << 1) | (1 << 10) | 1;
+	} else {
+		clock = 0;
+		data1 = ((ath5k_hw_bitswap((ath_channel - 24) / 2, 8) & 0xff) << 2)
+		    | (clock << 1) | (1 << 10) | 1;
+	}
+
+	AR5K_PHY_WRITE(hal, 0x27, (data1 & 0xff) | ((data0 & 0xff) << 8));
+	AR5K_PHY_WRITE(hal, 0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00));
+
+	return true;
+}
+
+/*
+ * Set channel on 5112
+ */
+bool
+ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel)
+{
+	u32 data, data0, data1, data2;
+	u16 c;
+
+	data = data0 = data1 = data2 = 0;
+	c = channel->freq;
+
+	/*
+	 * Set the channel on the RF5112 or newer
+	 */
+	if (c < 4800) {
+		if (!((c - 2224) % 5)) {
+			data0 = ((2 * (c - 704)) - 3040) / 10;
+			data1 = 1;
+		} else if (!((c - 2192) % 5)) {
+			data0 = ((2 * (c - 672)) - 3040) / 10;
+			data1 = 0;
+		} else
+			return false;
+
+		data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
+	} else {
+		if (!(c % 20) && c >= 5120) {
+			data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
+			data2 = ath5k_hw_bitswap(3, 2);
+		} else if (!(c % 10)) {
+			data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
+			data2 = ath5k_hw_bitswap(2, 2);
+		} else if (!(c % 5)) {
+			data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
+			data2 = ath5k_hw_bitswap(1, 2);
+		} else
+			return false;
+	}
+
+	data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
+
+	AR5K_PHY_WRITE(hal, 0x27, data & 0xff);
+	AR5K_PHY_WRITE(hal, 0x36, (data >> 8) & 0x7f);
+
+	return true;
+}
+
+/*
+ * Perform a PHY calibration
+ */
+bool
+ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel){
+
+	bool ret;
+
+	if (hal->ah_radio == AR5K_RF5110)
+		ret = ath5k_hw_rf5110_calibrate(hal,channel);
+	else
+		ret = ath5k_hw_rf511x_calibrate(hal,channel);
+
+	return ret;
+}
+/*
+ * Perform a PHY calibration on RF5110
+ */
+bool
+ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel)
+{
+	bool ret = true;
+	u32 phy_sig, phy_agc, phy_sat, beacon, noise_floor;
+	unsigned int i;
+
+#define AGC_DISABLE	{			\
+	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGC,	\
+		AR5K_PHY_AGC_DISABLE);		\
+	udelay(10);				\
+}
+
+#define AGC_ENABLE	{			\
+	AR5K_REG_DISABLE_BITS(hal, AR5K_PHY_AGC,	\
+	    AR5K_PHY_AGC_DISABLE);		\
+}
+
+	/*
+	 * Disable beacons and RX/TX queues, wait
+	 */
+	AR5K_REG_ENABLE_BITS(hal, AR5K_DIAG_SW_5210,
+	    AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
+	beacon = ath5k_hw_reg_read(hal, AR5K_BEACON_5210);
+	ath5k_hw_reg_write(hal, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
+
+	udelay(2300);
+
+	/*
+	 * Set the channel (with AGC turned off)
+	 */
+	AGC_DISABLE;
+	ret = ath5k_hw_channel(hal, channel);
+
+	/*
+	 * Activate PHY and wait
+	 */
+	ath5k_hw_reg_write(hal, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
+	mdelay(1);
+
+	AGC_ENABLE;
+
+	if (ret == false)
+		return ret;
+
+	/*
+	 * Calibrate the radio chip
+	 */
+
+	/* Remember normal state */
+	phy_sig = ath5k_hw_reg_read(hal, AR5K_PHY_SIG);
+	phy_agc = ath5k_hw_reg_read(hal, AR5K_PHY_AGCCOARSE);
+	phy_sat = ath5k_hw_reg_read(hal, AR5K_PHY_ADCSAT);
+
+	/* Update radio registers */
+	ath5k_hw_reg_write(hal, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
+		AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
+
+	ath5k_hw_reg_write(hal, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
+			AR5K_PHY_AGCCOARSE_LO)) |
+		AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
+		AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
+
+	ath5k_hw_reg_write(hal, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
+			AR5K_PHY_ADCSAT_THR)) |
+		AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
+		AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
+
+	udelay(20);
+
+	AGC_DISABLE;
+	ath5k_hw_reg_write(hal, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
+	AGC_ENABLE;
+
+	mdelay(1);
+
+	/*
+	 * Enable calibration and wait until completion
+	 */
+	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL,
+				AR5K_PHY_AGCCTL_CAL);
+
+	if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
+			AR5K_PHY_AGCCTL_CAL, 0, false)) {
+		AR5K_PRINTF("calibration timeout (%uMHz)\n",
+			channel->freq);
+		ret = false;
+	}
+
+	/* Reset to normal state */
+	ath5k_hw_reg_write(hal, phy_sig, AR5K_PHY_SIG);
+	ath5k_hw_reg_write(hal, phy_agc, AR5K_PHY_AGCCOARSE);
+	ath5k_hw_reg_write(hal, phy_sat, AR5K_PHY_ADCSAT);
+
+	if (ret == false)
+		return false;
+
+	/*
+ 	 * Enable noise floor calibration and wait until completion
+ 	 */
+	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL,
+				AR5K_PHY_AGCCTL_NF);
+
+	if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
+			AR5K_PHY_AGCCTL_NF, 0, false)) {
+		AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n",
+				channel->freq);
+		return false;
+	}
+
+	/* Wait until the noise floor is calibrated */
+	for (i = 20; i > 0; i--) {
+		mdelay(1);
+		noise_floor = ath5k_hw_reg_read(hal, AR5K_PHY_NF);
+
+		if (AR5K_PHY_NF_RVAL(noise_floor) &
+		AR5K_PHY_NF_ACTIVE)
+			noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
+	
+		if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
+			break;
+	}
+
+	if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
+		AR5K_PRINTF("noise floor calibration failed (%uMHz)\n",
+			channel->freq);
+		return false;
+	}
+
+
+	/*
+	 * Re-enable RX/TX and beacons
+	 */
+	AR5K_REG_DISABLE_BITS(hal, AR5K_DIAG_SW_5210,
+		AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
+	ath5k_hw_reg_write(hal, beacon, AR5K_BEACON_5210);
+
+#undef AGC_ENABLE
+#undef AGC_DISABLE
+
+	return true;
+}
+
+/*
+ * Perform a PHY calibration on RF5111/5112
+ */
+bool
+ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel)
+{
+	u32 i_pwr, q_pwr;
+	s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
+	AR5K_TRACE;
+
+	if (hal->ah_calibration == false ||
+	    ath5k_hw_reg_read(hal, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
+		goto done;
+
+	hal->ah_calibration = false;
+
+	iq_corr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_CORR);
+	i_pwr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_PWR_I);
+	q_pwr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_PWR_Q);
+	i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
+	q_coffd = q_pwr >> 6;
+
+	if (i_coffd == 0 || q_coffd == 0)
+		goto done;
+
+	i_coff = ((-iq_corr) / i_coffd) & 0x3f;
+	q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f;
+
+	/* Commit new IQ value */
+	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ,
+		AR5K_PHY_IQ_CORR_ENABLE |
+		((u32)q_coff) |
+		((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
+
+ done:
+	/* Start noise floor calibration */
+	AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL,
+		AR5K_PHY_AGCCTL_NF);
+
+	/* Request RF gain */
+	if (channel->val & CHANNEL_5GHZ) {
+		ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txpower.txp_max,
+			AR5K_PHY_PAPD_PROBE_TXPOWER) |
+			AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
+		hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED;
+	}
+
+	return true;
+}
+
+bool
+ath5k_hw_phy_disable(struct ath_hw *hal)
+{
+	AR5K_TRACE;
+	/*Just a try M.F.*/
+	ath5k_hw_reg_write(hal, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
+	return true;
+}
+
+void /*TODO:Boundary check*/
+ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant)
+{
+	AR5K_TRACE;
+	/*Just a try M.F.*/
+	if (hal->ah_version != AR5K_AR5210)
+		ath5k_hw_reg_write(hal, ant, AR5K_DEFAULT_ANTENNA);
+}
+
+unsigned int
+ath5k_hw_get_def_antenna(struct ath_hw *hal)
+{
+	AR5K_TRACE;
+	/*Just a try M.F.*/
+	if (hal->ah_version != AR5K_AR5210)
+		return ath5k_hw_reg_read(hal, AR5K_DEFAULT_ANTENNA);
+
+	return false; /*XXX: What do we return for 5210 ?*/
+}
+
+unsigned int
+ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
+    u32 first, u32 col, bool set)
+{
+	u32 mask, entry, last, data, shift, position;
+	s32 left;
+	int i;
+
+	data = 0;
+
+	if (rf == NULL)
+		/* should not happen */
+		return 0;
+
+	if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {
+		AR5K_PRINTF("invalid values at offset %u\n", offset);
+		return 0;
+	}
+
+	entry = ((first - 1) / 8) + offset;
+	position = (first - 1) % 8;
+
+	if (set == true)
+		data = ath5k_hw_bitswap(reg, bits);
+
+	for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
+		last = (position + left > 8) ? 8 : position + left;
+		mask = (((1 << last) - 1) ^ ((1 << position) - 1)) <<
+		    (col * 8);
+
+		if (set == true) {
+			rf[entry] &= ~mask;
+			rf[entry] |= ((data << position) << (col * 8)) & mask;
+			data >>= (8 - position);
+		} else {
+			data = (((rf[entry] & mask) >> (col * 8)) >>
+			    position) << shift;
+			shift += last - position;
+		}
+
+		left -= 8 - position;
+	}
+
+	data = set == true ? 1 : ath5k_hw_bitswap(data, bits);
+
+	return data;
+}
+
+u32
+ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal)
+{
+	u32 mix, step;
+	u32 *rf;
+
+	if (hal->ah_rf_banks == NULL)
+		return 0;
+
+	rf = hal->ah_rf_banks;
+	hal->ah_gain.g_f_corr = 0;
+
+	if (ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, false) != 1)
+		return 0;
+
+	step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, false);
+	mix = hal->ah_gain.g_step->gos_param[0];
+
+	switch (mix) {
+	case 3:
+		hal->ah_gain.g_f_corr = step * 2;
+		break;
+	case 2:
+		hal->ah_gain.g_f_corr = (step - 5) * 2;
+		break;
+	case 1:
+		hal->ah_gain.g_f_corr = step;
+		break;
+	default:
+		hal->ah_gain.g_f_corr = 0;
+		break;
+	}
+
+	return hal->ah_gain.g_f_corr;
+}
+
+bool
+ath5k_hw_rfregs_gain_readback(struct ath_hw *hal)
+{
+	u32 step, mix, level[4];
+	u32 *rf;
+
+	if (hal->ah_rf_banks == NULL)
+		return 0;
+
+	rf = hal->ah_rf_banks;
+
+	if (hal->ah_radio == AR5K_RF5111) {
+		step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
+		    0, 6, 37, 0, false);
+		level[0] = 0;
+		level[1] = (step == 0x3f) ? 0x32 : step + 4;
+		level[2] = (step != 0x3f) ? 0x40 : level[0];
+		level[3] = level[2] + 0x32;
+
+		hal->ah_gain.g_high = level[3] -
+		    (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
+		hal->ah_gain.g_low = level[0] +
+		    (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
+	} else {
+		mix = ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
+		    0, 1, 36, 0, false);
+		level[0] = level[2] = 0;
+
+		if (mix == 1) {
+			level[1] = level[3] = 83;
+		} else {
+			level[1] = level[3] = 107;
+			hal->ah_gain.g_high = 55;
+		}
+	}
+
+	return ((hal->ah_gain.g_current >= level[0] &&
+	    hal->ah_gain.g_current <= level[1]) ||
+	    (hal->ah_gain.g_current >= level[2] &&
+	    hal->ah_gain.g_current <= level[3]));
+}
+
+s32
+ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal)
+{
+	int ret = 0;
+	const struct ath5k_gain_opt *go;
+
+	go = hal->ah_radio == AR5K_RF5111 ?
+	    &rf5111_gain_opt : &rf5112_gain_opt;
+
+	hal->ah_gain.g_step = &go->go_step[hal->ah_gain.g_step_idx];
+
+	if (hal->ah_gain.g_current >= hal->ah_gain.g_high) {
+		if (hal->ah_gain.g_step_idx == 0)
+			return -1;
+		for (hal->ah_gain.g_target = hal->ah_gain.g_current;
+		    hal->ah_gain.g_target >=  hal->ah_gain.g_high &&
+		    hal->ah_gain.g_step_idx > 0;
+		    hal->ah_gain.g_step =
+		    &go->go_step[hal->ah_gain.g_step_idx]) {
+			hal->ah_gain.g_target -= 2 *
+			    (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain -
+			    hal->ah_gain.g_step->gos_gain);
+		}
+
+		ret = 1;
+		goto done;
+	}
+
+	if (hal->ah_gain.g_current <= hal->ah_gain.g_low) {
+		if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1))
+			return -2;
+		for (hal->ah_gain.g_target = hal->ah_gain.g_current;
+		    hal->ah_gain.g_target <=  hal->ah_gain.g_low &&
+		    hal->ah_gain.g_step_idx < (go->go_steps_count - 1);
+		    hal->ah_gain.g_step =
+		    &go->go_step[hal->ah_gain.g_step_idx]) {
+			hal->ah_gain.g_target -= 2 *
+			    (go->go_step[++(hal->ah_gain.g_step_idx)].gos_gain -
+			    hal->ah_gain.g_step->gos_gain);
+		}
+
+		ret = 2;
+		goto done;
+	}
+
+ done:
+#ifdef AR5K_DEBUG
+	AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n",
+	    ret,
+	    hal->ah_gain.g_step_idx,
+	    hal->ah_gain.g_current,
+	    hal->ah_gain.g_target);
+#endif
+
+	return ret;
+}
+
+/*
+ * Initialize RF
+ */
+bool
+ath5k_hw_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode)
+{
+	ath5k_rfgain_t *func = NULL;
+	bool ret;
+
+	if (hal->ah_radio == AR5K_RF5111) {
+		hal->ah_rf_banks_size = sizeof(rf5111_rf);
+		func = ath5k_hw_rf5111_rfregs;
+	} else if (hal->ah_radio == AR5K_RF5112) {
+		if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
+			hal->ah_rf_banks_size = sizeof(rf5112a_rf);
+		else
+		hal->ah_rf_banks_size = sizeof(rf5112_rf);
+		func = ath5k_hw_rf5112_rfregs;
+	} else
+		return false;
+
+	if (hal->ah_rf_banks == NULL) {
+		/* XXX do extra checks? */
+		if ((hal->ah_rf_banks = kmalloc(hal->ah_rf_banks_size,
+		    GFP_KERNEL)) == NULL) {
+			AR5K_PRINT("out of memory\n");
+			return false;
+		}
+	}
+
+	ret = (func)(hal, channel, mode);
+
+	if (ret == true)
+		hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
+
+	return ret;
+}
+
+/*
+ * Initialize RF5111
+ */
+bool
+ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode)
+{
+	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
+	const unsigned int rf_size = ARRAY_SIZE(rf5111_rf);
+	u32 *rf;
+	int i, obdb = -1, bank = -1;
+	u32 ee_mode;
+
+	AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
+
+	rf = hal->ah_rf_banks;
+
+	/* Copy values to modify them */
+	for (i = 0; i < rf_size; i++) {
+		if (rf5111_rf[i].rf_bank >=
+		    AR5K_RF5111_INI_RF_MAX_BANKS) {
+			AR5K_PRINT("invalid bank\n");
+			return false;
+		}
+
+		if (bank != rf5111_rf[i].rf_bank) {
+			bank = rf5111_rf[i].rf_bank;
+			hal->ah_offset[bank] = i;
+		}
+
+		rf[i] = rf5111_rf[i].rf_value[mode];
+	}
+
+	if (channel->val & CHANNEL_2GHZ) {
+		if (channel->val & CHANNEL_B)
+			ee_mode = AR5K_EEPROM_MODE_11B;
+		else
+			ee_mode = AR5K_EEPROM_MODE_11G;
+		obdb = 0;
+
+		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0],
+			ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
+			return false;
+
+		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0],
+			ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
+			return false;
+
+		obdb = 1;
+	} else {
+		/* For 11a, Turbo and XR */
+		ee_mode = AR5K_EEPROM_MODE_11A;
+		obdb = channel->freq >= 5725 ? 3 :
+		    (channel->freq >= 5500 ? 2 :
+			(channel->freq >= 5260 ? 1 :
+			    (channel->freq > 4000 ? 0 : -1)));
+
+		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
+			ee->ee_pwd_84, 1, 51, 3, true))
+			return false;
+
+		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
+			ee->ee_pwd_90, 1, 45, 3, true))
+			return false;
+	}
+
+	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
+		!ee->ee_xpd[ee_mode], 1, 95, 0, true))
+		return false;
+
+	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
+		ee->ee_x_gain[ee_mode], 4, 96, 0, true))
+		return false;
+
+	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
+		obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
+		return false;
+
+	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
+		obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
+		return false;
+
+	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
+		ee->ee_i_gain[ee_mode], 6, 29, 0, true))
+		return false;
+
+	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
+		ee->ee_xpd[ee_mode], 1, 4, 0, true))
+		return false;
+
+	/* Write RF values */
+	for (i = 0; i < rf_size; i++) {
+		AR5K_REG_WAIT(i);
+		ath5k_hw_reg_write(hal, rf[i], rf5111_rf[i].rf_register);
+	}
+
+	return true;
+}
+
+/*
+ * Initialize RF5112
+ */
+bool
+ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode)
+{
+	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
+	unsigned int rf_size;
+	u32 *rf;
+	int i, obdb = -1, bank = -1;
+	u32 ee_mode;
+	const struct ath5k_ini_rf *rf_ini;
+
+	AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
+
+	rf = hal->ah_rf_banks;
+
+	if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
+		rf_ini = rf5112a_rf;
+		rf_size = ARRAY_SIZE(rf5112a_rf);
+	} else {
+		rf_ini = rf5112_rf;
+		rf_size = ARRAY_SIZE(rf5112_rf);
+	}
+
+	/* Copy values to modify them */
+	for (i = 0; i < rf_size; i++) {
+		if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
+			AR5K_PRINT("invalid bank\n");
+			return false;
+		}
+
+		if (bank != rf_ini[i].rf_bank) {
+			bank = rf_ini[i].rf_bank;
+			hal->ah_offset[bank] = i;
+		}
+
+		rf[i] = rf_ini[i].rf_value[mode];
+	}
+
+	if (channel->val & CHANNEL_2GHZ) {
+		if (channel->val & CHANNEL_B)
+			ee_mode = AR5K_EEPROM_MODE_11B;
+		else
+			ee_mode = AR5K_EEPROM_MODE_11G;
+		obdb = 0;
+
+		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
+			ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
+			return false;
+
+		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
+			ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
+			return false;
+	} else {
+		/* For 11a, Turbo and XR */
+		ee_mode = AR5K_EEPROM_MODE_11A;
+		obdb = channel->freq >= 5725 ? 3 :
+		    (channel->freq >= 5500 ? 2 :
+			(channel->freq >= 5260 ? 1 :
+			    (channel->freq > 4000 ? 0 : -1)));
+
+		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
+			ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
+			return false;
+
+		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
+			ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
+			return false;
+	}
+
+#ifdef notyet
+	ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
+	    ee->ee_x_gain[ee_mode], 2, 270, 0, true);
+	ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
+	    ee->ee_x_gain[ee_mode], 2, 257, 0, true);
+#endif
+
+	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
+		ee->ee_xpd[ee_mode], 1, 302, 0, true))
+		return false;
+
+	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
+		ee->ee_i_gain[ee_mode], 6, 14, 0, true))
+		return false;
+
+	/* Write RF values */
+	for (i = 0; i < rf_size; i++)
+		ath5k_hw_reg_write(hal, rf[i], rf_ini[i].rf_register);
+
+	return true;
+}
+
+/*
+ * Initialize 5211 RF 
+ * TODO: is this needed ? i mean 5211 has a 5111 RF
+ * doesn't ar5k_rfregs work ?
+ */
+void
+ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int freq,
+    unsigned int ee_mode)
+{
+	struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
+	struct ath5k_ar5211_ini_rf rf[ARRAY_SIZE(ar5211_rf)];
+	u32 ob, db, obdb, xpds, xpdp, x_gain;
+	unsigned int i;
+
+	memcpy(rf, ar5211_rf, sizeof(rf));
+	obdb = 0;
+
+	if (freq == AR5K_INI_RFGAIN_2GHZ &&
+		hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_1) {
+			ob = ath5k_hw_bitswap(ee->ee_ob[ee_mode][0], 3);
+			db = ath5k_hw_bitswap(ee->ee_db[ee_mode][0], 3);
+		rf[25].rf_value[freq] =
+			((ob << 6) & 0xc0) | (rf[25].rf_value[freq] & ~0xc0);
+		rf[26].rf_value[freq] =
+			(((ob >> 2) & 0x1) | ((db << 1) & 0xe)) |
+			(rf[26].rf_value[freq] & ~0xf);
+	}
+
+	if (freq == AR5K_INI_RFGAIN_5GHZ) {
+		/* For 11a and Turbo */
+		obdb = channel->freq >= 5725 ? 3 :
+			(channel->freq >= 5500 ? 2 :
+				(channel->freq >= 5260 ? 1 :
+					(channel->freq > 4000 ? 0 : -1)));
+	}
+
+	ob = ee->ee_ob[ee_mode][obdb];
+	db = ee->ee_db[ee_mode][obdb];
+	x_gain = ee->ee_x_gain[ee_mode];
+	xpds = ee->ee_xpd[ee_mode];
+	xpdp = !xpds;
+
+	rf[11].rf_value[freq] = (rf[11].rf_value[freq] & ~0xc0) |
+		(((ath5k_hw_bitswap(x_gain, 4) << 7) | (xpdp << 6)) & 0xc0);
+	rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x7) |
+		((ath5k_hw_bitswap(x_gain, 4) >> 1) & 0x7);
+	rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x80) |
+		((ath5k_hw_bitswap(ob, 3) << 7) & 0x80);
+	rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x3) |
+		((ath5k_hw_bitswap(ob, 3) >> 1) & 0x3);
+	rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x1c) |
+		((ath5k_hw_bitswap(db, 3) << 2) & 0x1c);
+	rf[17].rf_value[freq] = (rf[17].rf_value[freq] & ~0x8) |
+		((xpds << 3) & 0x8);
+
+	for (i = 0; i < ARRAY_SIZE(rf); i++) {
+		AR5K_REG_WAIT(i);
+		ath5k_hw_reg_write(hal, rf[i].rf_value[freq],
+			(u32)rf[i].rf_register);
+	}
+
+	hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
+}
+
+bool
+ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq)
+{
+	int i;
+
+	switch (phy) {
+	case AR5K_INI_PHY_5111:
+	case AR5K_INI_PHY_5112:
+		break;
+	default:
+		return false;
+	}
+
+	switch (freq) {
+	case AR5K_INI_RFGAIN_2GHZ:
+	case AR5K_INI_RFGAIN_5GHZ:
+		break;
+	default:
+		return false;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ath5k_rfg); i++) {
+		AR5K_REG_WAIT(i);
+		ath5k_hw_reg_write(hal, ath5k_rfg[i].rfg_value[phy][freq],
+			(u32)ath5k_rfg[i].rfg_register);
+	}
+
+	return true;
+}
+
+enum ath5k_rfgain
+ath5k_hw_get_rf_gain(struct ath_hw *hal)
+{
+	u32 data, type;
+
+	AR5K_TRACE;
+
+	if (hal->ah_rf_banks == NULL || !hal->ah_gain.g_active ||
+			hal->ah_version <= AR5K_AR5211)
+		return AR5K_RFGAIN_INACTIVE;
+
+	if (hal->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED)
+		goto done;
+
+	data = ath5k_hw_reg_read(hal, AR5K_PHY_PAPD_PROBE);
+
+	if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
+		hal->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
+		type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
+
+		if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK)
+			hal->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR;
+
+		if (hal->ah_radio == AR5K_RF5112) {
+			ath5k_hw_rfregs_gainf_corr(hal);
+			hal->ah_gain.g_current =
+				hal->ah_gain.g_current >= hal->ah_gain.g_f_corr ?
+				(hal->ah_gain.g_current - hal->ah_gain.g_f_corr) :
+				0;
+		}
+
+		if (ath5k_hw_rfregs_gain_readback(hal) &&
+		AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) &&
+		ath5k_hw_rfregs_gain_adjust(hal))
+			hal->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE;
+	}
+
+ done:
+	return hal->ah_rf_gain;
+}
+
+/*
+ * TX power setup
+ */
+
+/*
+ * Initialize the tx power table (not fully implemented)
+ */
+static void ath5k_txpower_table(struct ath_hw *hal, struct ieee80211_channel *channel, s16 max_power)
+{
+	u16 txpower, *rates;
+	unsigned int i, min, max, n;
+
+	rates = hal->ah_txpower.txp_rates;
+
+	txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2;
+	if (max_power > txpower)
+		txpower = max_power > AR5K_TUNE_MAX_TXPOWER ?
+		    AR5K_TUNE_MAX_TXPOWER : max_power;
+
+	for (i = 0; i < AR5K_MAX_RATES; i++)
+		rates[i] = txpower;
+
+	/* XXX setup target powers by rate */
+
+	hal->ah_txpower.txp_min = rates[7];
+	hal->ah_txpower.txp_max = rates[0];
+	hal->ah_txpower.txp_ofdm = rates[0];
+
+	/* Calculate the power table */
+	n = ARRAY_SIZE(hal->ah_txpower.txp_pcdac);
+	min = AR5K_EEPROM_PCDAC_START;
+	max = AR5K_EEPROM_PCDAC_STOP;
+	for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP)
+		hal->ah_txpower.txp_pcdac[i] =
+#ifdef notyet
+		min + ((i * (max - min)) / n);
+#else
+		min;
+#endif
+}
+
+/*
+ * Set transmition power
+ */
+static int /*O.K. - txpower_table is unimplemented so this doesn't work*/
+ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int txpower)
+{
+	bool tpc = hal->ah_txpower.txp_tpc;
+	unsigned int i;
+
+	AR5K_TRACE;
+	if (txpower > AR5K_TUNE_MAX_TXPOWER) {
+		AR5K_PRINTF("invalid tx power: %u\n", txpower);
+		return -EINVAL;
+	}
+
+	/* Reset TX power values */
+	memset(&hal->ah_txpower, 0, sizeof(hal->ah_txpower));
+	hal->ah_txpower.txp_tpc = tpc;
+
+	/* Initialize TX power table */
+	ath5k_txpower_table(hal, channel, txpower);
+
+	/* 
+	 * Write TX power values
+	 */
+	for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
+		ath5k_hw_reg_write(hal,
+		      ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16)
+		    | ((((hal->ah_txpower.txp_pcdac[(i << 1)    ] << 8) | 0xff) & 0xffff)      ),
+			AR5K_PHY_PCDAC_TXPOWER(i));
+	}
+
+	ath5k_hw_reg_write(hal, AR5K_TXPOWER_OFDM(3, 24) |
+		AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
+		AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
+
+	ath5k_hw_reg_write(hal, AR5K_TXPOWER_OFDM(7, 24) |
+		AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
+		AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
+
+	ath5k_hw_reg_write(hal, AR5K_TXPOWER_CCK(10, 24) |
+		AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
+		AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
+
+	ath5k_hw_reg_write(hal, AR5K_TXPOWER_CCK(14, 24) |
+		AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
+		AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
+
+	if (hal->ah_txpower.txp_tpc == true) {
+		ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
+			AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
+	} else {
+		ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX |
+			AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
+	}
+
+	return 0;
+}
+
+int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power)
+{
+	/*Just a try M.F.*/
+	struct ieee80211_channel *channel = &hal->ah_current_channel;
+
+	AR5K_TRACE;
+#ifdef AR5K_DEBUG
+	AR5K_PRINTF("changing txpower to %d\n",power);
+#endif
+	return ath5k_hw_txpower(hal, channel, power);
+}
+
+
+
+
+/****************\
+  Misc functions
+\****************/
+
+void /*O.K.*/
+ath5k_hw_dump_state(struct ath_hw *hal)
+{
+#ifdef AR5K_DEBUG
+#define AR5K_PRINT_REGISTER(_x)						\
+	AR5K_PRINTF("(%s: %08x) ", #_x, ath5k_hw_reg_read(hal, AR5K_##_x));
+
+	AR5K_PRINT("MAC registers:\n");
+	AR5K_PRINT_REGISTER(CR);
+	AR5K_PRINT_REGISTER(CFG);
+	AR5K_PRINT_REGISTER(IER);
+	AR5K_PRINT_REGISTER(TXCFG);
+	AR5K_PRINT_REGISTER(RXCFG);
+	AR5K_PRINT_REGISTER(MIBC);
+	AR5K_PRINT_REGISTER(TOPS);
+	AR5K_PRINT_REGISTER(RXNOFRM);
+	AR5K_PRINT_REGISTER(RPGTO);
+	AR5K_PRINT_REGISTER(RFCNT);
+	AR5K_PRINT_REGISTER(MISC);
+	AR5K_PRINT_REGISTER(PISR);
+	AR5K_PRINT_REGISTER(SISR0);
+	AR5K_PRINT_REGISTER(SISR1);
+	AR5K_PRINT_REGISTER(SISR3);
+	AR5K_PRINT_REGISTER(SISR4);
+	AR5K_PRINT_REGISTER(DCM_ADDR);
+	AR5K_PRINT_REGISTER(DCM_DATA);
+	AR5K_PRINT_REGISTER(DCCFG);
+	AR5K_PRINT_REGISTER(CCFG);
+	AR5K_PRINT_REGISTER(CCFG_CUP);
+	AR5K_PRINT_REGISTER(CPC0);
+	AR5K_PRINT_REGISTER(CPC1);
+	AR5K_PRINT_REGISTER(CPC2);
+	AR5K_PRINT_REGISTER(CPCORN);
+	AR5K_PRINT_REGISTER(QCU_TXE);
+	AR5K_PRINT_REGISTER(QCU_TXD);
+	AR5K_PRINT_REGISTER(DCU_GBL_IFS_SIFS);
+	AR5K_PRINT_REGISTER(DCU_GBL_IFS_SLOT);
+	AR5K_PRINT_REGISTER(DCU_FP);
+	AR5K_PRINT_REGISTER(DCU_TXP);
+	AR5K_PRINT_REGISTER(DCU_TX_FILTER);
+	AR5K_PRINT_REGISTER(RC);
+	AR5K_PRINT_REGISTER(SCR);
+	AR5K_PRINT_REGISTER(INTPEND);
+	AR5K_PRINT_REGISTER(PCICFG);
+	AR5K_PRINT_REGISTER(GPIOCR);
+	AR5K_PRINT_REGISTER(GPIODO);
+	AR5K_PRINT_REGISTER(SREV);
+	AR5K_PRINT_REGISTER(EEPROM_BASE);
+	AR5K_PRINT_REGISTER(EEPROM_DATA);
+	AR5K_PRINT_REGISTER(EEPROM_CMD);
+	AR5K_PRINT_REGISTER(EEPROM_CFG);
+	AR5K_PRINT_REGISTER(PCU_MIN);
+	AR5K_PRINT_REGISTER(STA_ID0);
+	AR5K_PRINT_REGISTER(STA_ID1);
+	AR5K_PRINT_REGISTER(BSS_ID0);
+	AR5K_PRINT_REGISTER(SLOT_TIME);
+	AR5K_PRINT_REGISTER(TIME_OUT);
+	AR5K_PRINT_REGISTER(RSSI_THR);
+	AR5K_PRINT_REGISTER(BEACON);
+	AR5K_PRINT_REGISTER(CFP_PERIOD);
+	AR5K_PRINT_REGISTER(TIMER0);
+	AR5K_PRINT_REGISTER(TIMER2);
+	AR5K_PRINT_REGISTER(TIMER3);
+	AR5K_PRINT_REGISTER(CFP_DUR);
+	AR5K_PRINT_REGISTER(MCAST_FILTER0);
+	AR5K_PRINT_REGISTER(MCAST_FILTER1);
+	AR5K_PRINT_REGISTER(DIAG_SW);
+	AR5K_PRINT_REGISTER(TSF_U32);
+	AR5K_PRINT_REGISTER(ADDAC_TEST);
+	AR5K_PRINT_REGISTER(DEFAULT_ANTENNA);
+	AR5K_PRINT_REGISTER(LAST_TSTP);
+	AR5K_PRINT_REGISTER(NAV);
+	AR5K_PRINT_REGISTER(RTS_OK);
+	AR5K_PRINT_REGISTER(ACK_FAIL);
+	AR5K_PRINT_REGISTER(FCS_FAIL);
+	AR5K_PRINT_REGISTER(BEACON_CNT);
+	AR5K_PRINT_REGISTER(TSF_PARM);
+	AR5K_PRINT_REGISTER(RATE_DUR_0);
+	AR5K_PRINT_REGISTER(KEYTABLE_0);
+	AR5K_PRINT("\n");
+
+	AR5K_PRINT("PHY registers:\n");
+	AR5K_PRINT_REGISTER(PHY_TURBO);
+	AR5K_PRINT_REGISTER(PHY_AGC);
+	AR5K_PRINT_REGISTER(PHY_TIMING_3);
+	AR5K_PRINT_REGISTER(PHY_CHIP_ID);
+	AR5K_PRINT_REGISTER(PHY_AGCCTL);
+	AR5K_PRINT_REGISTER(PHY_NF);
+	AR5K_PRINT_REGISTER(PHY_SCR);
+	AR5K_PRINT_REGISTER(PHY_SLMT);
+	AR5K_PRINT_REGISTER(PHY_SCAL);
+	AR5K_PRINT_REGISTER(PHY_RX_DELAY);
+	AR5K_PRINT_REGISTER(PHY_IQ);
+	AR5K_PRINT_REGISTER(PHY_PAPD_PROBE);
+	AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE1);
+	AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE2);
+	AR5K_PRINT_REGISTER(PHY_FC);
+	AR5K_PRINT_REGISTER(PHY_RADAR);
+	AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_0);
+	AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_1);
+	AR5K_PRINT("\n");
+#endif
+}
+
+int ath5k_hw_get_capability(struct ath_hw *hal,
+		enum ath5k_capability_type cap_type,
+		u32 capability, u32 *result)
+{
+	AR5K_TRACE;
+
+	switch (cap_type) {
+	case AR5K_CAP_REG_DMN:
+		if (result){
+			*result = ath5k_get_regdomain(hal);
+			goto yes;
+		}
+	case AR5K_CAP_NUM_TXQUEUES: 
+		if (result) {
+			if (hal->ah_version == AR5K_AR5210)
+				*result = AR5K_NUM_TX_QUEUES_NOQCU;
+			else
+				*result = AR5K_NUM_TX_QUEUES;
+			goto yes;
+		}
+	case AR5K_CAP_VEOL:
+		goto yes;
+	case AR5K_CAP_COMPRESSION:
+		if (hal->ah_version == AR5K_AR5212)
+			goto yes;
+		else
+			goto no;
+	case AR5K_CAP_BURST:
+		goto yes;
+	case AR5K_CAP_TPC:
+		goto yes;
+	case AR5K_CAP_BSSIDMASK:
+		if (hal->ah_version == AR5K_AR5212)
+			goto yes;
+		else
+			goto no;
+	case AR5K_CAP_XR:
+		if (hal->ah_version == AR5K_AR5212)
+			goto yes;
+		else
+			goto no;
+	default: 
+		goto no;
+	}
+
+ no:
+	return -EINVAL;
+ yes:
+	return 0;
+	
+}
+
+int ath5k_hw_set_capability(struct ath_hw *hal,
+		enum ath5k_capability_type cap_type,
+		u32 capability, u32 setting)
+{
+	AR5K_TRACE;
+
+	return 0;
+}
+
+bool
+ath5k_hw_query_pspoll_support(struct ath_hw *hal)
+{
+	AR5K_TRACE;
+	if (hal->ah_version == AR5K_AR5210)
+		return(true);
+
+	return false;
+}
+
+bool
+ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid,
+    u16 assoc_id)
+{
+	AR5K_TRACE;
+	if (hal->ah_version == AR5K_AR5210) {
+		AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1,
+			AR5K_STA_ID1_NO_PSPOLL |
+			AR5K_STA_ID1_DEFAULT_ANTENNA);
+		return true;
+	}
+
+	return false;
+}
+
+bool
+ath5k_hw_disable_pspoll(struct ath_hw *hal)
+{
+	AR5K_TRACE;
+	if (hal->ah_version == AR5K_AR5210) {
+		AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1,
+			AR5K_STA_ID1_NO_PSPOLL |
+			AR5K_STA_ID1_DEFAULT_ANTENNA);
+		return true;
+	}
+
+	return false;
+}