The project is motivated by a live current research area concerning analysis and verification of complex (infinite-state) concurrent systems. It is the area of boundaries for algorithmic verification, where verification means checking equivalences of systems and their temporal logic properties. The main target of the proposed project (involving the PhD of the Jiri Srba) is to explore systematically the mentioned and related models and focus on characterization of decidable subclasses wrt usual equivalences.
Achieved results are supposed to be presented at foreign international and local conferences and will create a part of Jiri Srba's PhD thesis.
- Presentation at a foreign and a local conference
- Presentation at the Seminar on Informatics (FI)
- Technical report at FI MU Report Series
- Final report
Jiri Srba
Links
